93394f15ba
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
81 lines
2.8 KiB
C
81 lines
2.8 KiB
C
/* $NetBSD: uart.h,v 1.1 2007/03/20 08:52:02 dyoung Exp $ */
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/*-
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* Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* 3. The names of the authors may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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* PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
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* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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* OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ADMUART_H
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#define _ADMUART_H
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/* UART registers */
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#define UART_DR_REG 0x00
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#define UART_RSR_REG 0x04
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#define UART_RSR_FE 0x01
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#define UART_RSR_PE 0x02
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#define UART_RSR_BE 0x04
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#define UART_RSR_OE 0x08
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#define UART_ECR_REG 0x04
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#define UART_ECR_RSR 0x80
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#define UART_LCR_H_REG 0x08
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#define UART_LCR_H_FEN 0x10
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#define UART_LCR_M_REG 0x0c
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#define UART_LCR_L_REG 0x10
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#define UART_CR_REG 0x14
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#define UART_CR_PORT_EN 0x01
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#define UART_CR_SIREN 0x02
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#define UART_CR_SIRLP 0x04
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#define UART_CR_MODEM_STATUS_INT_EN 0x08
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#define UART_CR_RX_INT_EN 0x10
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#define UART_CR_TX_INT_EN 0x20
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#define UART_CR_RX_TIMEOUT_INT_EN 0x40
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#define UART_CR_LOOPBACK_EN 0x80
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#define UART_FR_REG 0x18
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#define UART_FR_CTS 0x01
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#define UART_FR_DSR 0x02
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#define UART_FR_DCD 0x04
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#define UART_FR_BUSY 0x08
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#define UART_FR_RX_FIFO_EMPTY 0x10
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#define UART_FR_TX_FIFO_FULL 0x20
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#define UART_FR_RX_FIFO_FULL 0x40
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#define UART_FR_TX_FIFO_EMPTY 0x80
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#define UART_IR_REG 0x1c
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#define UART_IR_MODEM_STATUS_INT 0x01
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#define UART_IR_RX_INT 0x02
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#define UART_IR_TX_INT 0x04
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#define UART_IR_RX_TIMEOUT_INT 0x08
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#define UART_IR_INT_MASK 0x0f
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#define UART_IR_UICR 0x80
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#define UART_ILPR_REG 0x20
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/* UART interrupts */
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int uart_cnattach(void);
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#endif /* _ADMUART_H */
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