8ce07fe72e
was previously available on gpio.4 to their respectives pages. Add the cross references on gpioctl.8. Approved by: adrian (mentor)
144 lines
4.3 KiB
Groff
144 lines
4.3 KiB
Groff
.\" Copyright (c) 2013, Sean Bruno <sbruno@freebsd.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd November 5, 2013
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.Dt GPIO 4
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.Os
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.Sh NAME
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.Nm gpiobus
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.Nd GPIO bus system
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.Sh SYNOPSIS
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To compile these devices into your kernel and use the device hints, place the
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following lines in your kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device gpio"
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.Cd "device gpioc"
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.Cd "device gpioiic"
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.Cd "device gpioled"
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.Ed
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.Pp
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Additional device entries for the
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.Li ARM
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architecure include:
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.Bd -ragged -offset indent
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.Cd "device a10_gpio"
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.Cd "device bcm_gpio"
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.Cd "device imx51_gpio"
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.Cd "device lpcgpio"
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.Cd "device mv_gpio"
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.Cd "device ti_gpio"
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.Cd "device gpio_avila"
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.Cd "device gpio_cambria"
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.Cd "device zy7_gpio"
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.Cd "device pxagpio"
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.Ed
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.Pp
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Additional device entries for the
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.Li MIPS
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architecure include:
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.Bd -ragged -offset indent
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.Cd "device ar71xxx_gpio"
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.Cd "device octeon_gpio"
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.Cd "device rt305_gpio"
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.Ed
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.Pp
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Additional device entries for the
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.Li POWERPC
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architecure include:
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.Bd -ragged -offset indent
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.Cd "device wiigpio"
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.Cd "device macgpio"
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.Ed
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.Sh DESCRIPTION
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The
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.Em gpiobus
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system provides a simple interface to the GPIO pins that are usually
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available on embedded architectures and can provide bit banging style
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devices to the system.
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.Pp
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The acronym
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.Li GPIO
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means
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.Dq General-Purpose Input/Output.
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.Pp
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The BUS physically consists of multiple pins that can be configured
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for input/output, IRQ delivery, SDA/SCL
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.Em iicbus
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use, etc.
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.Pp
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On some embedded architechtures (like MIPS), discovery of the bus and
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configuration of the pins is done via
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.Xr device.hints 5
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in the platform's kernel
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.Xr config 5
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file.
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.Pp
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On some others (like ARM), where
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.Xr FDT 4
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is used to describe the device tree, the bus discovery is done via the DTS
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passed to the kernel, being either statically compiled in, or by a variety
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of ways where the boot loader (or Open Firmware enabled system) passes the
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DTS blob to kernel at boot.
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.Pp
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The following are only provided by the
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.Cd ar71xx_gpio
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driver.
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.Bl -tag -width ".Va hint.gpioiic.%d.atXXX"
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.It Va hint.gpio.%d.pinmask
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This is a bitmask of pins on the gpio board that we would like to expose
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for use to the host o/s.
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To expose pin 0, 4 and 7, use the bitmask of
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10010001 converted to the hexadecimal value 0x0091.
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.It Va hint.gpio.%d.pinon
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This is a bitmask of pins on the gpio board that will be set to ON at host
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start.
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To set pin 2, 5 and 13 to be set ON at boot, use the bitmask of
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10000000010010 converted to the hexadecimal value 0x2012.
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.It Va hint.gpio.function_set
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.It Va hint.gpio.function_clear
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These are a bitmask of pins that will remap a pin to handle a specific
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function (USB, UART TX/RX, etc) in the Atheros function registers.
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This is mainly used to set/clear functions that we need when they are setup or
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not setup by uBoot.
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.El
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.Pp
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Simply put, each pin of the GPIO interface is connected to an input/output
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of some device in a system.
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.Sh SEE ALSO
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.Xr gpioiic 4 ,
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.Xr gpioled 4 ,
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.Xr iicbus 4 ,
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.Xr gpioctl 8
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.Sh HISTORY
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The
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.Nm
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manual page first appeared in
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.Fx 10.0 .
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.Sh AUTHORS
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This
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manual page was written by
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.An Sean Bruno Aq sbruno@FreeBSD.org .
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