5fcaec1a0b
Reviewed by: gallatin, rpokala MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D24922
677 lines
20 KiB
C
677 lines
20 KiB
C
/*-
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* Broadcom NetXtreme-C/E network driver.
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*
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* Copyright (c) 2016 Broadcom, All Rights Reserved.
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* The term Broadcom refers to Broadcom Limited and/or its subsidiaries
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#ifndef _BNXT_H
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#define _BNXT_H
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#include <sys/param.h>
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#include <sys/socket.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <net/ethernet.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/iflib.h>
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#include "hsi_struct_def.h"
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/* PCI IDs */
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#define BROADCOM_VENDOR_ID 0x14E4
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#define BCM57301 0x16c8
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#define BCM57302 0x16c9
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#define BCM57304 0x16ca
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#define BCM57311 0x16ce
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#define BCM57312 0x16cf
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#define BCM57314 0x16df
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#define BCM57402 0x16d0
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#define BCM57402_NPAR 0x16d4
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#define BCM57404 0x16d1
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#define BCM57404_NPAR 0x16e7
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#define BCM57406 0x16d2
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#define BCM57406_NPAR 0x16e8
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#define BCM57407 0x16d5
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#define BCM57407_NPAR 0x16ea
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#define BCM57407_SFP 0x16e9
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#define BCM57412 0x16d6
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#define BCM57412_NPAR1 0x16de
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#define BCM57412_NPAR2 0x16eb
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#define BCM57414 0x16d7
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#define BCM57414_NPAR1 0x16ec
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#define BCM57414_NPAR2 0x16ed
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#define BCM57416 0x16d8
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#define BCM57416_NPAR1 0x16ee
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#define BCM57416_NPAR2 0x16ef
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#define BCM57416_SFP 0x16e3
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#define BCM57417 0x16d9
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#define BCM57417_NPAR1 0x16c0
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#define BCM57417_NPAR2 0x16cc
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#define BCM57417_SFP 0x16e2
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#define BCM57454 0x1614
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#define BCM58700 0x16cd
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#define NETXTREME_C_VF1 0x16cb
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#define NETXTREME_C_VF2 0x16e1
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#define NETXTREME_C_VF3 0x16e5
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#define NETXTREME_E_VF1 0x16c1
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#define NETXTREME_E_VF2 0x16d3
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#define NETXTREME_E_VF3 0x16dc
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/* Maximum numbers of RX and TX descriptors. iflib requires this to be a power
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* of two. The hardware has no particular limitation. */
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#define BNXT_MAX_RXD ((INT32_MAX >> 1) + 1)
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#define BNXT_MAX_TXD ((INT32_MAX >> 1) + 1)
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#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \
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CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \
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CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP)
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#define BNXT_MAX_MTU 9000
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#define BNXT_RSS_HASH_TYPE_TCPV4 0
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#define BNXT_RSS_HASH_TYPE_UDPV4 1
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#define BNXT_RSS_HASH_TYPE_IPV4 2
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#define BNXT_RSS_HASH_TYPE_TCPV6 3
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#define BNXT_RSS_HASH_TYPE_UDPV6 4
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#define BNXT_RSS_HASH_TYPE_IPV6 5
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#define BNXT_GET_RSS_PROFILE_ID(rss_hash_type) ((rss_hash_type >> 1) & 0x1F)
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#define BNXT_NO_MORE_WOL_FILTERS 0xFFFF
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#define bnxt_wol_supported(softc) (!((softc)->flags & BNXT_FLAG_VF) && \
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((softc)->flags & BNXT_FLAG_WOL_CAP ))
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/* Completion related defines */
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#define CMP_VALID(cmp, v_bit) \
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((!!(((struct cmpl_base *)(cmp))->info3_v & htole32(CMPL_BASE_V))) == !!(v_bit) )
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#define NEXT_CP_CONS_V(ring, cons, v_bit) do { \
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if (__predict_false(++(cons) == (ring)->ring_size)) \
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((cons) = 0, (v_bit) = !v_bit); \
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} while (0)
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#define RING_NEXT(ring, idx) (__predict_false(idx + 1 == (ring)->ring_size) ? \
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0 : idx + 1)
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#define CMPL_PREFETCH_NEXT(cpr, idx) \
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__builtin_prefetch(&((struct cmpl_base *)(cpr)->ring.vaddr)[((idx) +\
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(CACHE_LINE_SIZE / sizeof(struct cmpl_base))) & \
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((cpr)->ring.ring_size - 1)])
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/*
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* If we update the index, a write barrier is needed after the write to ensure
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* the completion ring has space before the RX/TX ring does. Since we can't
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* make the RX and AG doorbells covered by the same barrier without remapping
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* MSI-X vectors, we create the barrier over the enture doorbell bar.
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* TODO: Remap the MSI-X vectors to allow a barrier to only cover the doorbells
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* for a single ring group.
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*
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* A barrier of just the size of the write is used to ensure the ordering
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* remains correct and no writes are lost.
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*/
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#define BNXT_CP_DISABLE_DB(ring) do { \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \
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BUS_SPACE_BARRIER_WRITE); \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, 0, \
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(ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \
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bus_space_write_4((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, \
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htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_MASK)); \
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} while (0)
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#define BNXT_CP_ENABLE_DB(ring) do { \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \
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BUS_SPACE_BARRIER_WRITE); \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, 0, \
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(ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \
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bus_space_write_4((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, \
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htole32(CMPL_DOORBELL_KEY_CMPL)); \
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} while (0)
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#define BNXT_CP_IDX_ENABLE_DB(ring, cons) do { \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \
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BUS_SPACE_BARRIER_WRITE); \
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bus_space_write_4((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, \
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htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \
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(cons))); \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, 0, \
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(ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \
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} while (0)
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#define BNXT_CP_IDX_DISABLE_DB(ring, cons) do { \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \
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BUS_SPACE_BARRIER_WRITE); \
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bus_space_write_4((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, \
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htole32(CMPL_DOORBELL_KEY_CMPL | CMPL_DOORBELL_IDX_VALID | \
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CMPL_DOORBELL_MASK | (cons))); \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, 0, \
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(ring)->softc->doorbell_bar.size, BUS_SPACE_BARRIER_WRITE); \
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} while (0)
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#define BNXT_TX_DB(ring, idx) do { \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \
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BUS_SPACE_BARRIER_WRITE); \
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bus_space_write_4( \
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(ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, \
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(ring)->doorbell, htole32(TX_DOORBELL_KEY_TX | (idx))); \
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} while (0)
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#define BNXT_RX_DB(ring, idx) do { \
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bus_space_barrier((ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, (ring)->doorbell, 4, \
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BUS_SPACE_BARRIER_WRITE); \
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bus_space_write_4( \
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(ring)->softc->doorbell_bar.tag, \
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(ring)->softc->doorbell_bar.handle, \
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(ring)->doorbell, htole32(RX_DOORBELL_KEY_RX | (idx))); \
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} while (0)
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/* Lock macros */
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#define BNXT_HWRM_LOCK_INIT(_softc, _name) \
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mtx_init(&(_softc)->hwrm_lock, _name, "BNXT HWRM Lock", MTX_DEF)
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#define BNXT_HWRM_LOCK(_softc) mtx_lock(&(_softc)->hwrm_lock)
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#define BNXT_HWRM_UNLOCK(_softc) mtx_unlock(&(_softc)->hwrm_lock)
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#define BNXT_HWRM_LOCK_DESTROY(_softc) mtx_destroy(&(_softc)->hwrm_lock)
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#define BNXT_HWRM_LOCK_ASSERT(_softc) mtx_assert(&(_softc)->hwrm_lock, \
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MA_OWNED)
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#define BNXT_IS_FLOW_CTRL_CHANGED(link_info) \
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((link_info->last_flow_ctrl.tx != link_info->flow_ctrl.tx) || \
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(link_info->last_flow_ctrl.rx != link_info->flow_ctrl.rx) || \
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(link_info->last_flow_ctrl.autoneg != link_info->flow_ctrl.autoneg))
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/* Chip info */
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#define BNXT_TSO_SIZE UINT16_MAX
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#define min_t(type, x, y) ({ \
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type __min1 = (x); \
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type __min2 = (y); \
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__min1 < __min2 ? __min1 : __min2; })
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#define max_t(type, x, y) ({ \
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type __max1 = (x); \
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type __max2 = (y); \
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__max1 > __max2 ? __max1 : __max2; })
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#define clamp_t(type, _x, min, max) min_t(type, max_t(type, _x, min), max)
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#define BNXT_IFMEDIA_ADD(supported, fw_speed, ifm_speed) do { \
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if ((supported) & HWRM_PORT_PHY_QCFG_OUTPUT_SUPPORT_ ## fw_speed) \
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ifmedia_add(softc->media, IFM_ETHER | (ifm_speed), 0, NULL); \
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} while(0)
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#define BNXT_MIN_FRAME_SIZE 52 /* Frames must be padded to this size for some A0 chips */
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/* NVRAM access */
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enum bnxt_nvm_directory_type {
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BNX_DIR_TYPE_UNUSED = 0,
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BNX_DIR_TYPE_PKG_LOG = 1,
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BNX_DIR_TYPE_UPDATE = 2,
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BNX_DIR_TYPE_CHIMP_PATCH = 3,
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BNX_DIR_TYPE_BOOTCODE = 4,
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BNX_DIR_TYPE_VPD = 5,
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BNX_DIR_TYPE_EXP_ROM_MBA = 6,
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BNX_DIR_TYPE_AVS = 7,
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BNX_DIR_TYPE_PCIE = 8,
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BNX_DIR_TYPE_PORT_MACRO = 9,
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BNX_DIR_TYPE_APE_FW = 10,
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BNX_DIR_TYPE_APE_PATCH = 11,
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BNX_DIR_TYPE_KONG_FW = 12,
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BNX_DIR_TYPE_KONG_PATCH = 13,
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BNX_DIR_TYPE_BONO_FW = 14,
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BNX_DIR_TYPE_BONO_PATCH = 15,
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BNX_DIR_TYPE_TANG_FW = 16,
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BNX_DIR_TYPE_TANG_PATCH = 17,
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BNX_DIR_TYPE_BOOTCODE_2 = 18,
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BNX_DIR_TYPE_CCM = 19,
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BNX_DIR_TYPE_PCI_CFG = 20,
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BNX_DIR_TYPE_TSCF_UCODE = 21,
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BNX_DIR_TYPE_ISCSI_BOOT = 22,
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BNX_DIR_TYPE_ISCSI_BOOT_IPV6 = 24,
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BNX_DIR_TYPE_ISCSI_BOOT_IPV4N6 = 25,
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BNX_DIR_TYPE_ISCSI_BOOT_CFG6 = 26,
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BNX_DIR_TYPE_EXT_PHY = 27,
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BNX_DIR_TYPE_SHARED_CFG = 40,
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BNX_DIR_TYPE_PORT_CFG = 41,
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BNX_DIR_TYPE_FUNC_CFG = 42,
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BNX_DIR_TYPE_MGMT_CFG = 48,
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BNX_DIR_TYPE_MGMT_DATA = 49,
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BNX_DIR_TYPE_MGMT_WEB_DATA = 50,
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BNX_DIR_TYPE_MGMT_WEB_META = 51,
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BNX_DIR_TYPE_MGMT_EVENT_LOG = 52,
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BNX_DIR_TYPE_MGMT_AUDIT_LOG = 53
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};
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enum bnxnvm_pkglog_field_index {
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BNX_PKG_LOG_FIELD_IDX_INSTALLED_TIMESTAMP = 0,
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BNX_PKG_LOG_FIELD_IDX_PKG_DESCRIPTION = 1,
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BNX_PKG_LOG_FIELD_IDX_PKG_VERSION = 2,
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BNX_PKG_LOG_FIELD_IDX_PKG_TIMESTAMP = 3,
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BNX_PKG_LOG_FIELD_IDX_PKG_CHECKSUM = 4,
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BNX_PKG_LOG_FIELD_IDX_INSTALLED_ITEMS = 5,
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BNX_PKG_LOG_FIELD_IDX_INSTALLED_MASK = 6
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};
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#define BNX_DIR_ORDINAL_FIRST 0
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#define BNX_DIR_EXT_NONE 0
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struct bnxt_bar_info {
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struct resource *res;
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bus_space_tag_t tag;
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bus_space_handle_t handle;
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bus_size_t size;
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int rid;
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};
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struct bnxt_flow_ctrl {
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bool rx;
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bool tx;
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bool autoneg;
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};
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struct bnxt_link_info {
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uint8_t media_type;
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uint8_t transceiver;
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uint8_t phy_addr;
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uint8_t phy_link_status;
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uint8_t wire_speed;
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uint8_t loop_back;
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uint8_t link_up;
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uint8_t last_link_up;
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uint8_t duplex;
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uint8_t last_duplex;
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struct bnxt_flow_ctrl flow_ctrl;
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struct bnxt_flow_ctrl last_flow_ctrl;
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uint8_t duplex_setting;
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uint8_t auto_mode;
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#define PHY_VER_LEN 3
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uint8_t phy_ver[PHY_VER_LEN];
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uint8_t phy_type;
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uint16_t link_speed;
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uint16_t support_speeds;
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uint16_t auto_link_speeds;
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uint16_t auto_link_speed;
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uint16_t force_link_speed;
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uint32_t preemphasis;
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/* copy of requested setting */
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uint8_t autoneg;
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#define BNXT_AUTONEG_SPEED 1
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#define BNXT_AUTONEG_FLOW_CTRL 2
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uint8_t req_duplex;
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uint16_t req_link_speed;
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};
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enum bnxt_cp_type {
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BNXT_DEFAULT,
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BNXT_TX,
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BNXT_RX,
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BNXT_SHARED
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};
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struct bnxt_cos_queue {
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uint8_t id;
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uint8_t profile;
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};
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struct bnxt_func_info {
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uint32_t fw_fid;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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uint16_t max_rsscos_ctxs;
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uint16_t max_cp_rings;
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uint16_t max_tx_rings;
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uint16_t max_rx_rings;
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uint16_t max_hw_ring_grps;
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uint16_t max_irqs;
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uint16_t max_l2_ctxs;
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uint16_t max_vnics;
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uint16_t max_stat_ctxs;
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};
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struct bnxt_pf_info {
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#define BNXT_FIRST_PF_FID 1
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#define BNXT_FIRST_VF_FID 128
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uint8_t port_id;
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uint32_t first_vf_id;
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uint16_t active_vfs;
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uint16_t max_vfs;
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uint32_t max_encap_records;
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uint32_t max_decap_records;
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uint32_t max_tx_em_flows;
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uint32_t max_tx_wm_flows;
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uint32_t max_rx_em_flows;
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uint32_t max_rx_wm_flows;
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unsigned long *vf_event_bmap;
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uint16_t hwrm_cmd_req_pages;
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void *hwrm_cmd_req_addr[4];
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bus_addr_t hwrm_cmd_req_dma_addr[4];
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};
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struct bnxt_vf_info {
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uint16_t fw_fid;
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uint8_t mac_addr[ETHER_ADDR_LEN];
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uint16_t max_rsscos_ctxs;
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uint16_t max_cp_rings;
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uint16_t max_tx_rings;
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uint16_t max_rx_rings;
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uint16_t max_hw_ring_grps;
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uint16_t max_l2_ctxs;
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uint16_t max_irqs;
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uint16_t max_vnics;
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uint16_t max_stat_ctxs;
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uint32_t vlan;
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#define BNXT_VF_QOS 0x1
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#define BNXT_VF_SPOOFCHK 0x2
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#define BNXT_VF_LINK_FORCED 0x4
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#define BNXT_VF_LINK_UP 0x8
|
|
uint32_t flags;
|
|
uint32_t func_flags; /* func cfg flags */
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|
uint32_t min_tx_rate;
|
|
uint32_t max_tx_rate;
|
|
void *hwrm_cmd_req_addr;
|
|
bus_addr_t hwrm_cmd_req_dma_addr;
|
|
};
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|
|
|
|
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#define BNXT_PF(softc) (!((softc)->flags & BNXT_FLAG_VF))
|
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#define BNXT_VF(softc) ((softc)->flags & BNXT_FLAG_VF)
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|
|
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struct bnxt_vlan_tag {
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SLIST_ENTRY(bnxt_vlan_tag) next;
|
|
uint16_t tpid;
|
|
uint16_t tag;
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|
};
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|
|
|
struct bnxt_vnic_info {
|
|
uint16_t id;
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|
uint16_t def_ring_grp;
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|
uint16_t cos_rule;
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|
uint16_t lb_rule;
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|
uint16_t mru;
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|
|
|
uint32_t rx_mask;
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|
bool vlan_only;
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|
struct iflib_dma_info mc_list;
|
|
int mc_list_count;
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|
#define BNXT_MAX_MC_ADDRS 16
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|
|
|
uint32_t flags;
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|
#define BNXT_VNIC_FLAG_DEFAULT 0x01
|
|
#define BNXT_VNIC_FLAG_BD_STALL 0x02
|
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#define BNXT_VNIC_FLAG_VLAN_STRIP 0x04
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|
|
|
uint64_t filter_id;
|
|
uint32_t flow_id;
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|
|
|
uint16_t rss_id;
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|
uint32_t rss_hash_type;
|
|
uint8_t rss_hash_key[HW_HASH_KEY_SIZE];
|
|
struct iflib_dma_info rss_hash_key_tbl;
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|
struct iflib_dma_info rss_grp_tbl;
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|
SLIST_HEAD(vlan_head, bnxt_vlan_tag) vlan_tags;
|
|
struct iflib_dma_info vlan_tag_list;
|
|
};
|
|
|
|
struct bnxt_grp_info {
|
|
uint16_t stats_ctx;
|
|
uint16_t grp_id;
|
|
uint16_t rx_ring_id;
|
|
uint16_t cp_ring_id;
|
|
uint16_t ag_ring_id;
|
|
};
|
|
|
|
struct bnxt_ring {
|
|
uint64_t paddr;
|
|
vm_offset_t doorbell;
|
|
caddr_t vaddr;
|
|
struct bnxt_softc *softc;
|
|
uint32_t ring_size; /* Must be a power of two */
|
|
uint16_t id; /* Logical ID */
|
|
uint16_t phys_id;
|
|
struct bnxt_full_tpa_start *tpa_start;
|
|
};
|
|
|
|
struct bnxt_cp_ring {
|
|
struct bnxt_ring ring;
|
|
struct if_irq irq;
|
|
uint32_t cons;
|
|
bool v_bit; /* Value of valid bit */
|
|
struct ctx_hw_stats *stats;
|
|
uint32_t stats_ctx_id;
|
|
uint32_t last_idx; /* Used by RX rings only
|
|
* set to the last read pidx
|
|
*/
|
|
};
|
|
|
|
struct bnxt_full_tpa_start {
|
|
struct rx_tpa_start_cmpl low;
|
|
struct rx_tpa_start_cmpl_hi high;
|
|
};
|
|
|
|
/* All the version information for the part */
|
|
#define BNXT_VERSTR_SIZE (3*3+2+1) /* ie: "255.255.255\0" */
|
|
#define BNXT_NAME_SIZE 17
|
|
struct bnxt_ver_info {
|
|
uint8_t hwrm_if_major;
|
|
uint8_t hwrm_if_minor;
|
|
uint8_t hwrm_if_update;
|
|
char hwrm_if_ver[BNXT_VERSTR_SIZE];
|
|
char driver_hwrm_if_ver[BNXT_VERSTR_SIZE];
|
|
char hwrm_fw_ver[BNXT_VERSTR_SIZE];
|
|
char mgmt_fw_ver[BNXT_VERSTR_SIZE];
|
|
char netctrl_fw_ver[BNXT_VERSTR_SIZE];
|
|
char roce_fw_ver[BNXT_VERSTR_SIZE];
|
|
char phy_ver[BNXT_VERSTR_SIZE];
|
|
char pkg_ver[64];
|
|
|
|
char hwrm_fw_name[BNXT_NAME_SIZE];
|
|
char mgmt_fw_name[BNXT_NAME_SIZE];
|
|
char netctrl_fw_name[BNXT_NAME_SIZE];
|
|
char roce_fw_name[BNXT_NAME_SIZE];
|
|
char phy_vendor[BNXT_NAME_SIZE];
|
|
char phy_partnumber[BNXT_NAME_SIZE];
|
|
|
|
uint16_t chip_num;
|
|
uint8_t chip_rev;
|
|
uint8_t chip_metal;
|
|
uint8_t chip_bond_id;
|
|
uint8_t chip_type;
|
|
|
|
uint8_t hwrm_min_major;
|
|
uint8_t hwrm_min_minor;
|
|
uint8_t hwrm_min_update;
|
|
|
|
struct sysctl_ctx_list ver_ctx;
|
|
struct sysctl_oid *ver_oid;
|
|
};
|
|
|
|
struct bnxt_nvram_info {
|
|
uint16_t mfg_id;
|
|
uint16_t device_id;
|
|
uint32_t sector_size;
|
|
uint32_t size;
|
|
uint32_t reserved_size;
|
|
uint32_t available_size;
|
|
|
|
struct sysctl_ctx_list nvm_ctx;
|
|
struct sysctl_oid *nvm_oid;
|
|
};
|
|
|
|
struct bnxt_func_qcfg {
|
|
uint16_t alloc_completion_rings;
|
|
uint16_t alloc_tx_rings;
|
|
uint16_t alloc_rx_rings;
|
|
uint16_t alloc_vnics;
|
|
};
|
|
|
|
struct bnxt_hw_lro {
|
|
uint16_t enable;
|
|
uint16_t is_mode_gro;
|
|
uint16_t max_agg_segs;
|
|
uint16_t max_aggs;
|
|
uint32_t min_agg_len;
|
|
};
|
|
|
|
struct bnxt_softc {
|
|
device_t dev;
|
|
if_ctx_t ctx;
|
|
if_softc_ctx_t scctx;
|
|
if_shared_ctx_t sctx;
|
|
struct ifmedia *media;
|
|
|
|
struct bnxt_bar_info hwrm_bar;
|
|
struct bnxt_bar_info doorbell_bar;
|
|
struct bnxt_link_info link_info;
|
|
#define BNXT_FLAG_VF 0x0001
|
|
#define BNXT_FLAG_NPAR 0x0002
|
|
#define BNXT_FLAG_WOL_CAP 0x0004
|
|
#define BNXT_FLAG_SHORT_CMD 0x0008
|
|
uint32_t flags;
|
|
uint32_t total_msix;
|
|
|
|
struct bnxt_func_info func;
|
|
struct bnxt_func_qcfg fn_qcfg;
|
|
struct bnxt_pf_info pf;
|
|
struct bnxt_vf_info vf;
|
|
|
|
uint16_t hwrm_cmd_seq;
|
|
uint32_t hwrm_cmd_timeo; /* milliseconds */
|
|
struct iflib_dma_info hwrm_cmd_resp;
|
|
struct iflib_dma_info hwrm_short_cmd_req_addr;
|
|
/* Interrupt info for HWRM */
|
|
struct if_irq irq;
|
|
struct mtx hwrm_lock;
|
|
uint16_t hwrm_max_req_len;
|
|
|
|
#define BNXT_MAX_QUEUE 8
|
|
uint8_t max_tc;
|
|
struct bnxt_cos_queue q_info[BNXT_MAX_QUEUE];
|
|
|
|
uint64_t admin_ticks;
|
|
struct iflib_dma_info hw_rx_port_stats;
|
|
struct iflib_dma_info hw_tx_port_stats;
|
|
struct rx_port_stats *rx_port_stats;
|
|
struct tx_port_stats *tx_port_stats;
|
|
|
|
int num_cp_rings;
|
|
|
|
struct bnxt_ring *tx_rings;
|
|
struct bnxt_cp_ring *tx_cp_rings;
|
|
struct iflib_dma_info tx_stats;
|
|
int ntxqsets;
|
|
|
|
struct bnxt_vnic_info vnic_info;
|
|
struct bnxt_ring *ag_rings;
|
|
struct bnxt_ring *rx_rings;
|
|
struct bnxt_cp_ring *rx_cp_rings;
|
|
struct bnxt_grp_info *grp_info;
|
|
struct iflib_dma_info rx_stats;
|
|
int nrxqsets;
|
|
|
|
struct bnxt_cp_ring def_cp_ring;
|
|
struct iflib_dma_info def_cp_ring_mem;
|
|
struct grouptask def_cp_task;
|
|
|
|
struct sysctl_ctx_list hw_stats;
|
|
struct sysctl_oid *hw_stats_oid;
|
|
struct sysctl_ctx_list hw_lro_ctx;
|
|
struct sysctl_oid *hw_lro_oid;
|
|
struct sysctl_ctx_list flow_ctrl_ctx;
|
|
struct sysctl_oid *flow_ctrl_oid;
|
|
|
|
struct bnxt_ver_info *ver_info;
|
|
struct bnxt_nvram_info *nvm_info;
|
|
bool wol;
|
|
struct bnxt_hw_lro hw_lro;
|
|
uint8_t wol_filter_id;
|
|
uint16_t rx_coal_usecs;
|
|
uint16_t rx_coal_usecs_irq;
|
|
uint16_t rx_coal_frames;
|
|
uint16_t rx_coal_frames_irq;
|
|
uint16_t tx_coal_usecs;
|
|
uint16_t tx_coal_usecs_irq;
|
|
uint16_t tx_coal_frames;
|
|
uint16_t tx_coal_frames_irq;
|
|
|
|
#define BNXT_USEC_TO_COAL_TIMER(x) ((x) * 25 / 2)
|
|
#define BNXT_DEF_STATS_COAL_TICKS 1000000
|
|
#define BNXT_MIN_STATS_COAL_TICKS 250000
|
|
#define BNXT_MAX_STATS_COAL_TICKS 1000000
|
|
|
|
};
|
|
|
|
struct bnxt_filter_info {
|
|
STAILQ_ENTRY(bnxt_filter_info) next;
|
|
uint64_t fw_l2_filter_id;
|
|
#define INVALID_MAC_INDEX ((uint16_t)-1)
|
|
uint16_t mac_index;
|
|
|
|
/* Filter Characteristics */
|
|
uint32_t flags;
|
|
uint32_t enables;
|
|
uint8_t l2_addr[ETHER_ADDR_LEN];
|
|
uint8_t l2_addr_mask[ETHER_ADDR_LEN];
|
|
uint16_t l2_ovlan;
|
|
uint16_t l2_ovlan_mask;
|
|
uint16_t l2_ivlan;
|
|
uint16_t l2_ivlan_mask;
|
|
uint8_t t_l2_addr[ETHER_ADDR_LEN];
|
|
uint8_t t_l2_addr_mask[ETHER_ADDR_LEN];
|
|
uint16_t t_l2_ovlan;
|
|
uint16_t t_l2_ovlan_mask;
|
|
uint16_t t_l2_ivlan;
|
|
uint16_t t_l2_ivlan_mask;
|
|
uint8_t tunnel_type;
|
|
uint16_t mirror_vnic_id;
|
|
uint32_t vni;
|
|
uint8_t pri_hint;
|
|
uint64_t l2_filter_id_hint;
|
|
};
|
|
|
|
/* Function declarations */
|
|
void bnxt_report_link(struct bnxt_softc *softc);
|
|
bool bnxt_check_hwrm_version(struct bnxt_softc *softc);
|
|
|
|
#endif /* _BNXT_H */
|