278 lines
6.8 KiB
C
278 lines
6.8 KiB
C
/*-
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* Copyright (c) 2005 Olivier Houchard. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/time.h>
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#include <sys/bus.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <arm/at91/at91rm92reg.h>
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#include <arm/at91/at91var.h>
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#include <arm/at91/at91_streg.h>
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static struct at91st_softc {
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bus_space_tag_t sc_st;
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bus_space_handle_t sc_sh;
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device_t sc_dev;
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eventhandler_tag sc_wet; /* watchdog event handler tag */
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} *timer_softc;
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#define RD4(off) \
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bus_space_read_4(timer_softc->sc_st, timer_softc->sc_sh, (off))
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#define WR4(off, val) \
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bus_space_write_4(timer_softc->sc_st, timer_softc->sc_sh, (off), (val))
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static void at91st_watchdog(void *, u_int, int *);
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static inline int
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st_crtr(void)
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{
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int cur1, cur2;
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do {
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cur1 = RD4(ST_CRTR);
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cur2 = RD4(ST_CRTR);
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} while (cur1 != cur2);
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return (cur1);
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}
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static unsigned at91st_get_timecount(struct timecounter *tc);
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static struct timecounter at91st_timecounter = {
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at91st_get_timecount, /* get_timecount */
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NULL, /* no poll_pps */
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#ifdef SKYEYE_WORKAROUNDS
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0xffffffffu, /* counter_mask */
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#else
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0xfffffu, /* counter_mask */
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#endif
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32768, /* frequency */
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"AT91RM9200 timer", /* name */
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1000 /* quality */
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};
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static int
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at91st_probe(device_t dev)
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{
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device_set_desc(dev, "ST");
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return (0);
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}
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static int
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at91st_attach(device_t dev)
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{
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struct at91_softc *sc = device_get_softc(device_get_parent(dev));
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timer_softc = device_get_softc(dev);
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timer_softc->sc_st = sc->sc_st;
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timer_softc->sc_dev = dev;
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if (bus_space_subregion(sc->sc_st, sc->sc_sh, AT91RM92_ST_BASE,
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AT91RM92_ST_SIZE, &timer_softc->sc_sh) != 0)
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panic("couldn't subregion timer registers");
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/*
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* Real time counter increments every clock cycle, need to set before
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* initializing clocks so that DELAY works.
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*/
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WR4(ST_RTMR, 1);
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/* Disable all interrupts */
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WR4(ST_IDR, 0xffffffff);
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/* disable watchdog timer */
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WR4(ST_WDMR, 0);
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timer_softc->sc_wet = EVENTHANDLER_REGISTER(watchdog_list,
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at91st_watchdog, dev, 0);
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device_printf(dev,
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"watchdog registered, timeout intervall max. 64 sec\n");
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return (0);
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}
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static device_method_t at91st_methods[] = {
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DEVMETHOD(device_probe, at91st_probe),
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DEVMETHOD(device_attach, at91st_attach),
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{0, 0},
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};
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static driver_t at91st_driver = {
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"at91_st",
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at91st_methods,
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sizeof(struct at91st_softc),
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};
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static devclass_t at91st_devclass;
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DRIVER_MODULE(at91_st, atmelarm, at91st_driver, at91st_devclass, 0, 0);
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#ifdef SKYEYE_WORKAROUNDS
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static unsigned long tot_count = 0;
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#endif
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static unsigned
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at91st_get_timecount(struct timecounter *tc)
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{
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#ifdef SKYEYE_WORKAROUNDS
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return (tot_count);
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#else
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return (st_crtr());
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#endif
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}
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/*
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* t below is in a weird unit. The watchdog is set to 2^t
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* nanoseconds. Since our watchdog timer can't really do that too
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* well, we approximate it by assuming that the timeout interval for
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* the lsb is 2^22 ns, which is 4.194ms. This is an overestimation of
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* the actual time (3.906ms), but close enough for watchdogging.
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* These approximations, though a violation of the spec, improve the
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* performance of the application which typically specifies things as
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* WD_TO_32SEC. In that last case, we'd wait 32s before the wdog
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* reset. The spec says we should wait closer to 34s, but given how
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* it is likely to be used, and the extremely coarse nature time
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* interval, I think this is the best solution.
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*/
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static void
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at91st_watchdog(void *argp, u_int cmd, int *error)
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{
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uint32_t wdog;
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int t;
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t = cmd & WD_INTERVAL;
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if (cmd > 0 && t >= 22 && t <= 37) {
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wdog = (1 << (t - 22)) | ST_WDMR_RSTEN;
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*error = 0;
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} else {
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wdog = 0;
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if (cmd > 0)
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*error = EINVAL;
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}
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WR4(ST_WDMR, wdog);
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WR4(ST_CR, ST_CR_WDRST);
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}
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static void
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clock_intr(void *arg)
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{
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struct trapframe *fp = arg;
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/* The interrupt is shared, so we have to make sure it's for us. */
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if (RD4(ST_SR) & ST_SR_PITS) {
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#ifdef SKYEYE_WORKAROUNDS
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tot_count += 32768 / hz;
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#endif
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hardclock(TRAPF_USERMODE(fp), TRAPF_PC(fp));
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}
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}
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void
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cpu_initclocks(void)
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{
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int rel_value;
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struct resource *irq;
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int rid = 0;
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void *ih;
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device_t dev = timer_softc->sc_dev;
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rel_value = 32768 / hz;
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if (rel_value < 1)
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rel_value = 1;
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if (32768 % hz) {
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printf("Cannot get %d Hz clock; using %dHz\n", hz, 32768 / rel_value);
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hz = 32768 / rel_value;
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tick = 1000000 / hz;
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}
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/* Disable all interrupts.<2E>*/
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WR4(ST_IDR, 0xffffffff);
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/* The system timer shares the system irq (1) */
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irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 1, 1, 1,
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RF_ACTIVE | RF_SHAREABLE);
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if (!irq)
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panic("Unable to allocate irq for the system timer");
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else
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bus_setup_intr(dev, irq, INTR_TYPE_CLK | INTR_FAST,
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clock_intr, NULL, &ih);
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WR4(ST_PIMR, rel_value);
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/* Enable PITS interrupts. */
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WR4(ST_IER, ST_SR_PITS);
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tc_init(&at91st_timecounter);
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}
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void
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DELAY(int n)
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{
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uint32_t start, end, cur;
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start = st_crtr();
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n = (n * 1000) / 32768;
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if (n <= 0)
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n = 1;
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end = (start + n) & ST_CRTR_MASK;
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cur = start;
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if (start > end) {
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while (cur >= start || cur < end)
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cur = st_crtr();
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} else {
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while (cur < end)
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cur = st_crtr();
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}
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}
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void
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cpu_reset(void)
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{
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/*
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* Reset the CPU by programmig the watchdog timer to reset the
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* CPU after 128 'slow' clocks, or about ~4ms. Loop until
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* the reset happens for safety.
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*/
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WR4(ST_WDMR, ST_WDMR_RSTEN | 2);
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WR4(ST_CR, ST_CR_WDRST);
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while (1)
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continue;
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}
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void
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cpu_startprofclock(void)
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{
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}
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void
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cpu_stopprofclock(void)
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{
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}
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