efc5c4420a
libunwind and openmp to the upstream release_80 branch r363030 (effectively, 8.0.1 rc2). The 8.0.1 release should follow this within a week or so. MFC after: 2 weeks
242 lines
8.2 KiB
C++
242 lines
8.2 KiB
C++
//===-- SparcRegisterInfo.cpp - SPARC Register Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SPARC implementation of the TargetRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcRegisterInfo.h"
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#include "Sparc.h"
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#include "SparcMachineFunctionInfo.h"
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#include "SparcSubtarget.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define GET_REGINFO_TARGET_DESC
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#include "SparcGenRegisterInfo.inc"
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static cl::opt<bool>
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ReserveAppRegisters("sparc-reserve-app-registers", cl::Hidden, cl::init(false),
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cl::desc("Reserve application registers (%g2-%g4)"));
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SparcRegisterInfo::SparcRegisterInfo() : SparcGenRegisterInfo(SP::O7) {}
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const MCPhysReg*
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SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
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return CSR_SaveList;
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}
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const uint32_t *
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SparcRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
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CallingConv::ID CC) const {
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return CSR_RegMask;
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}
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const uint32_t*
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SparcRegisterInfo::getRTCallPreservedMask(CallingConv::ID CC) const {
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return RTCSR_RegMask;
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}
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BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
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BitVector Reserved(getNumRegs());
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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// FIXME: G1 reserved for now for large imm generation by frame code.
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Reserved.set(SP::G1);
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// G1-G4 can be used in applications.
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if (ReserveAppRegisters) {
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Reserved.set(SP::G2);
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Reserved.set(SP::G3);
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Reserved.set(SP::G4);
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}
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// G5 is not reserved in 64 bit mode.
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if (!Subtarget.is64Bit())
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Reserved.set(SP::G5);
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Reserved.set(SP::O6);
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Reserved.set(SP::I6);
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Reserved.set(SP::I7);
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Reserved.set(SP::G0);
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Reserved.set(SP::G6);
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Reserved.set(SP::G7);
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// Also reserve the register pair aliases covering the above
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// registers, with the same conditions.
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Reserved.set(SP::G0_G1);
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if (ReserveAppRegisters)
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Reserved.set(SP::G2_G3);
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if (ReserveAppRegisters || !Subtarget.is64Bit())
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Reserved.set(SP::G4_G5);
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Reserved.set(SP::O6_O7);
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Reserved.set(SP::I6_I7);
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Reserved.set(SP::G6_G7);
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// Unaliased double registers are not available in non-V9 targets.
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if (!Subtarget.isV9()) {
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for (unsigned n = 0; n != 16; ++n) {
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for (MCRegAliasIterator AI(SP::D16 + n, this, true); AI.isValid(); ++AI)
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Reserved.set(*AI);
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}
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}
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// Reserve ASR1-ASR31
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for (unsigned n = 0; n < 31; n++)
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Reserved.set(SP::ASR1 + n);
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return Reserved;
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}
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const TargetRegisterClass*
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SparcRegisterInfo::getPointerRegClass(const MachineFunction &MF,
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unsigned Kind) const {
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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return Subtarget.is64Bit() ? &SP::I64RegsRegClass : &SP::IntRegsRegClass;
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}
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static void replaceFI(MachineFunction &MF, MachineBasicBlock::iterator II,
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MachineInstr &MI, const DebugLoc &dl,
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unsigned FIOperandNum, int Offset, unsigned FramePtr) {
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// Replace frame index with a frame pointer reference.
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.getOperand(FIOperandNum).ChangeToRegister(FramePtr, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
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return;
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}
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const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
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// FIXME: it would be better to scavenge a register here instead of
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// reserving G1 all of the time.
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if (Offset >= 0) {
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// Emit nonnegaive immediates with sethi + or.
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// sethi %hi(Offset), %g1
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// add %g1, %fp, %g1
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// Insert G1+%lo(offset) into the user.
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HI22(Offset));
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// Emit G1 = G1 + I6
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(LO10(Offset));
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return;
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}
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// Emit Negative numbers with sethi + xor
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// sethi %hix(Offset), %g1
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// xor %g1, %lox(offset), %g1
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// add %g1, %fp, %g1
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// Insert: G1 + 0 into the user.
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
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.addImm(HIX22(Offset));
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
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.addReg(SP::G1).addImm(LOX10(Offset));
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
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.addReg(FramePtr);
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// Insert: G1+%lo(offset) into the user.
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MI.getOperand(FIOperandNum).ChangeToRegister(SP::G1, false);
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MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
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}
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void
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SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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int SPAdj, unsigned FIOperandNum,
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RegScavenger *RS) const {
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assert(SPAdj == 0 && "Unexpected");
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MachineInstr &MI = *II;
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DebugLoc dl = MI.getDebugLoc();
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int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
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MachineFunction &MF = *MI.getParent()->getParent();
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const SparcSubtarget &Subtarget = MF.getSubtarget<SparcSubtarget>();
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const SparcFrameLowering *TFI = getFrameLowering(MF);
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unsigned FrameReg;
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int Offset;
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Offset = TFI->getFrameIndexReference(MF, FrameIndex, FrameReg);
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Offset += MI.getOperand(FIOperandNum + 1).getImm();
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if (!Subtarget.isV9() || !Subtarget.hasHardQuad()) {
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if (MI.getOpcode() == SP::STQFri) {
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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unsigned SrcReg = MI.getOperand(2).getReg();
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unsigned SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
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unsigned SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::STDFri))
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.addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
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replaceFI(MF, *StMI, *StMI, dl, 0, Offset, FrameReg);
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MI.setDesc(TII.get(SP::STDFri));
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MI.getOperand(2).setReg(SrcOddReg);
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Offset += 8;
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} else if (MI.getOpcode() == SP::LDQFri) {
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const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
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unsigned DestReg = MI.getOperand(0).getReg();
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unsigned DestEvenReg = getSubReg(DestReg, SP::sub_even64);
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unsigned DestOddReg = getSubReg(DestReg, SP::sub_odd64);
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MachineInstr *StMI =
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BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
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.addReg(FrameReg).addImm(0);
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replaceFI(MF, *StMI, *StMI, dl, 1, Offset, FrameReg);
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MI.setDesc(TII.get(SP::LDDFri));
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MI.getOperand(0).setReg(DestOddReg);
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Offset += 8;
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}
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}
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replaceFI(MF, II, MI, dl, FIOperandNum, Offset, FrameReg);
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}
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unsigned SparcRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
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return SP::I6;
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}
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// Sparc has no architectural need for stack realignment support,
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// except that LLVM unfortunately currently implements overaligned
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// stack objects by depending upon stack realignment support.
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// If that ever changes, this can probably be deleted.
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bool SparcRegisterInfo::canRealignStack(const MachineFunction &MF) const {
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if (!TargetRegisterInfo::canRealignStack(MF))
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return false;
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// Sparc always has a fixed frame pointer register, so don't need to
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// worry about needing to reserve it. [even if we don't have a frame
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// pointer for our frame, it still cannot be used for other things,
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// or register window traps will be SADNESS.]
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// If there's a reserved call frame, we can use SP to access locals.
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if (getFrameLowering(MF)->hasReservedCallFrame(MF))
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return true;
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// Otherwise, we'd need a base pointer, but those aren't implemented
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// for SPARC at the moment.
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return false;
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}
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