635 lines
16 KiB
C
635 lines
16 KiB
C
/*-
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (C) 2001 Benno Rice
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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* $NetBSD: machdep.c,v 1.74.2.1 2000/11/01 16:13:48 tv Exp $
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*/
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/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_compat.h"
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#include "opt_ddb.h"
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#include "opt_kstack_pages.h"
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#include "opt_msgbuf.h"
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#include <sys/cdefs.h>
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#include <sys/types.h>
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <sys/time.h>
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#include <sys/bio.h>
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#include <sys/buf.h>
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#include <sys/bus.h>
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#include <sys/cons.h>
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#include <sys/cpu.h>
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#include <sys/kdb.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <sys/exec.h>
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#include <sys/ktr.h>
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#include <sys/syscallsubr.h>
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#include <sys/sysproto.h>
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#include <sys/signalvar.h>
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#include <sys/sysent.h>
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#include <sys/imgact.h>
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#include <sys/msgbuf.h>
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#include <sys/ptrace.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_page.h>
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#include <vm/vm_object.h>
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#include <vm/vm_pager.h>
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#include <machine/cpu.h>
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#include <machine/kdb.h>
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#include <machine/reg.h>
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#include <machine/vmparam.h>
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#include <machine/spr.h>
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#include <machine/hid.h>
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#include <machine/psl.h>
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#include <machine/trap.h>
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#include <machine/md_var.h>
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#include <machine/mmuvar.h>
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#include <machine/sigframe.h>
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#include <machine/metadata.h>
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#include <machine/platform.h>
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#include <sys/linker.h>
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#include <sys/reboot.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/openfirm.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#ifdef DDB
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extern vm_offset_t ksym_start, ksym_end;
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#endif
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#ifdef DEBUG
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#define debugf(fmt, args...) printf(fmt, ##args)
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#else
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#define debugf(fmt, args...)
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#endif
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extern unsigned char kernel_text[];
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extern unsigned char _etext[];
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extern unsigned char _edata[];
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extern unsigned char __bss_start[];
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extern unsigned char __sbss_start[];
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extern unsigned char __sbss_end[];
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extern unsigned char _end[];
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extern void dcache_enable(void);
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extern void dcache_inval(void);
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extern void icache_enable(void);
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extern void icache_inval(void);
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struct kva_md_info kmi;
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struct pcpu __pcpu[MAXCPU];
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struct trapframe frame0;
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int cold = 1;
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long realmem = 0;
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long Maxmem = 0;
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char machine[] = "powerpc";
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SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "");
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int cacheline_size = 32;
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SYSCTL_INT(_machdep, CPU_CACHELINE, cacheline_size,
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CTLFLAG_RD, &cacheline_size, 0, "");
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int hw_direct_map = 0;
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static void cpu_e500_startup(void *);
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SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_e500_startup, NULL);
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void print_kernel_section_addr(void);
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void print_kenv(void);
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u_int e500_init(u_int32_t, u_int32_t, void *);
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static void
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cpu_e500_startup(void *dummy)
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{
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int indx, size;
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/* Initialise the decrementer-based clock. */
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decr_init();
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/* Good {morning,afternoon,evening,night}. */
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cpu_setup(PCPU_GET(cpuid));
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printf("real memory = %ld (%ld MB)\n", ptoa(physmem),
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ptoa(physmem) / 1048576);
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realmem = physmem;
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/* Display any holes after the first chunk of extended memory. */
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if (bootverbose) {
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printf("Physical memory chunk(s):\n");
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for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
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size = phys_avail[indx + 1] - phys_avail[indx];
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printf("0x%08x - 0x%08x, %d bytes (%ld pages)\n",
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phys_avail[indx], phys_avail[indx + 1] - 1,
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size, size / PAGE_SIZE);
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}
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}
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vm_ksubmap_init(&kmi);
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printf("avail memory = %ld (%ld MB)\n", ptoa(cnt.v_free_count),
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ptoa(cnt.v_free_count) / 1048576);
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/* Set up buffers, so they can be used to read disk labels. */
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bufinit();
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vm_pager_bufferinit();
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}
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static char *
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kenv_next(char *cp)
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{
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if (cp != NULL) {
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while (*cp != 0)
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cp++;
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cp++;
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if (*cp == 0)
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cp = NULL;
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}
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return (cp);
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}
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void
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print_kenv(void)
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{
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int len;
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char *cp;
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debugf("loader passed (static) kenv:\n");
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if (kern_envp == NULL) {
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debugf(" no env, null ptr\n");
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return;
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}
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debugf(" kern_envp = 0x%08x\n", (u_int32_t)kern_envp);
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len = 0;
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for (cp = kern_envp; cp != NULL; cp = kenv_next(cp))
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debugf(" %x %s\n", (u_int32_t)cp, cp);
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}
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void
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print_kernel_section_addr(void)
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{
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debugf("kernel image addresses:\n");
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debugf(" kernel_text = 0x%08x\n", (uint32_t)kernel_text);
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debugf(" _etext (sdata) = 0x%08x\n", (uint32_t)_etext);
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debugf(" _edata = 0x%08x\n", (uint32_t)_edata);
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debugf(" __sbss_start = 0x%08x\n", (uint32_t)__sbss_start);
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debugf(" __sbss_end = 0x%08x\n", (uint32_t)__sbss_end);
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debugf(" __sbss_start = 0x%08x\n", (uint32_t)__bss_start);
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debugf(" _end = 0x%08x\n", (uint32_t)_end);
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}
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u_int
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e500_init(u_int32_t startkernel, u_int32_t endkernel, void *mdp)
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{
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struct pcpu *pc;
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void *kmdp;
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vm_offset_t dtbp, end;
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uint32_t csr;
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kmdp = NULL;
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end = endkernel;
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dtbp = (vm_offset_t)NULL;
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/*
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* Parse metadata and fetch parameters.
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*/
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if (mdp != NULL) {
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preload_metadata = mdp;
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kmdp = preload_search_by_type("elf kernel");
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if (kmdp != NULL) {
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boothowto = MD_FETCH(kmdp, MODINFOMD_HOWTO, int);
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kern_envp = MD_FETCH(kmdp, MODINFOMD_ENVP, char *);
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dtbp = MD_FETCH(kmdp, MODINFOMD_DTBP, vm_offset_t);
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end = MD_FETCH(kmdp, MODINFOMD_KERNEND, vm_offset_t);
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#ifdef DDB
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ksym_start = MD_FETCH(kmdp, MODINFOMD_SSYM, uintptr_t);
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ksym_end = MD_FETCH(kmdp, MODINFOMD_ESYM, uintptr_t);
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#endif
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}
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} else {
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/*
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* We should scream but how? Cannot even output anything...
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*/
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/*
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* FIXME add return value and handle in the locore so we can
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* return to the loader maybe? (this seems not very easy to
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* restore everything as the TLB have all been reprogrammed
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* in the locore etc...)
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*/
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while (1);
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}
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if (OF_install(OFW_FDT, 0) == FALSE)
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while (1);
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if (OF_init((void *)dtbp) != 0)
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while (1);
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if (fdt_immr_addr(CCSRBAR_VA) != 0)
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while (1);
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OF_interpret("perform-fixup", 0);
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/* Initialize TLB1 handling */
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tlb1_init(fdt_immr_pa);
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/* Reset Time Base */
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mttb(0);
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/* Init params/tunables that can be overridden by the loader. */
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init_param1();
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/* Start initializing proc0 and thread0. */
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proc_linkup0(&proc0, &thread0);
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thread0.td_frame = &frame0;
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/* Set up per-cpu data and store the pointer in SPR general 0. */
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pc = &__pcpu[0];
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pcpu_init(pc, 0, sizeof(struct pcpu));
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pc->pc_curthread = &thread0;
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__asm __volatile("mtsprg 0, %0" :: "r"(pc));
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/* Initialize system mutexes. */
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mutex_init();
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/* Initialize the console before printing anything. */
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cninit();
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/* Print out some debug info... */
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debugf("e500_init: console initialized\n");
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debugf(" arg1 startkernel = 0x%08x\n", startkernel);
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debugf(" arg2 endkernel = 0x%08x\n", endkernel);
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debugf(" arg3 mdp = 0x%08x\n", (u_int32_t)mdp);
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debugf(" end = 0x%08x\n", (u_int32_t)end);
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debugf(" boothowto = 0x%08x\n", boothowto);
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debugf(" kernel ccsrbar = 0x%08x\n", CCSRBAR_VA);
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debugf(" MSR = 0x%08x\n", mfmsr());
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debugf(" HID0 = 0x%08x\n", mfspr(SPR_HID0));
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debugf(" HID1 = 0x%08x\n", mfspr(SPR_HID1));
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debugf(" BUCSR = 0x%08x\n", mfspr(SPR_BUCSR));
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__asm __volatile("msync; isync");
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csr = ccsr_read4(OCP85XX_L2CTL);
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debugf(" L2CTL = 0x%08x\n", csr);
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debugf(" dtbp = 0x%08x\n", (uint32_t)dtbp);
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print_kernel_section_addr();
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print_kenv();
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//tlb1_print_entries();
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//tlb1_print_tlbentries();
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kdb_init();
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#ifdef KDB
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if (boothowto & RB_KDB)
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kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
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#endif
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/* Initialise platform module */
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platform_probe_and_attach();
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/* Initialise virtual memory. */
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pmap_mmu_install(MMU_TYPE_BOOKE, 0);
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pmap_bootstrap(startkernel, end);
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debugf("MSR = 0x%08x\n", mfmsr());
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//tlb1_print_entries();
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//tlb1_print_tlbentries();
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/* Initialize params/tunables that are derived from memsize. */
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init_param2(physmem);
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/* Finish setting up thread0. */
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thread0.td_pcb = (struct pcb *)
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((thread0.td_kstack + thread0.td_kstack_pages * PAGE_SIZE -
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sizeof(struct pcb)) & ~15);
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bzero((void *)thread0.td_pcb, sizeof(struct pcb));
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pc->pc_curpcb = thread0.td_pcb;
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/* Initialise the message buffer. */
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msgbufinit(msgbufp, MSGBUF_SIZE);
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/* Enable Machine Check interrupt. */
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mtmsr(mfmsr() | PSL_ME);
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isync();
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/* Enable D-cache if applicable */
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csr = mfspr(SPR_L1CSR0);
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if ((csr & L1CSR0_DCE) == 0) {
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dcache_inval();
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dcache_enable();
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}
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csr = mfspr(SPR_L1CSR0);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR0_DCE) == 0)
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printf("L1 D-cache %sabled\n",
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(csr & L1CSR0_DCE) ? "en" : "dis");
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/* Enable L1 I-cache if applicable. */
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csr = mfspr(SPR_L1CSR1);
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if ((csr & L1CSR1_ICE) == 0) {
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icache_inval();
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icache_enable();
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}
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csr = mfspr(SPR_L1CSR1);
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if ((boothowto & RB_VERBOSE) != 0 || (csr & L1CSR1_ICE) == 0)
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printf("L1 I-cache %sabled\n",
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(csr & L1CSR1_ICE) ? "en" : "dis");
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debugf("e500_init: SP = 0x%08x\n", ((uintptr_t)thread0.td_pcb - 16) & ~15);
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debugf("e500_init: e\n");
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return (((uintptr_t)thread0.td_pcb - 16) & ~15);
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}
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#define RES_GRANULE 32
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extern uint32_t tlb0_miss_locks[];
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/* Initialise a struct pcpu. */
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void
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cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t sz)
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{
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pcpu->pc_tid_next = TID_MIN;
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#ifdef SMP
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uint32_t *ptr;
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int words_per_gran = RES_GRANULE / sizeof(uint32_t);
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ptr = &tlb0_miss_locks[cpuid * words_per_gran];
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pcpu->pc_booke_tlb_lock = ptr;
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*ptr = MTX_UNOWNED;
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*(ptr + 1) = 0; /* recurse counter */
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#endif
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}
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/*
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* Flush the D-cache for non-DMA I/O so that the I-cache can
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* be made coherent later.
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*/
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void
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cpu_flush_dcache(void *ptr, size_t len)
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{
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/* TBD */
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}
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/*
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* cpu_idle
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*
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* Set Wait state enable.
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*/
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void
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cpu_idle (int busy)
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{
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register_t msr;
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msr = mfmsr();
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#ifdef INVARIANTS
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if ((msr & PSL_EE) != PSL_EE) {
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struct thread *td = curthread;
|
|
printf("td msr %x\n", td->td_md.md_saved_msr);
|
|
panic("ints disabled in idleproc!");
|
|
}
|
|
#endif
|
|
|
|
/* Freescale E500 core RM section 6.4.1. */
|
|
msr = msr | PSL_WE;
|
|
__asm __volatile("msync; mtmsr %0; isync" :: "r" (msr));
|
|
}
|
|
|
|
int
|
|
cpu_idle_wakeup(int cpu)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
spinlock_enter(void)
|
|
{
|
|
struct thread *td;
|
|
|
|
td = curthread;
|
|
if (td->td_md.md_spinlock_count == 0)
|
|
td->td_md.md_saved_msr = intr_disable();
|
|
td->td_md.md_spinlock_count++;
|
|
critical_enter();
|
|
}
|
|
|
|
void
|
|
spinlock_exit(void)
|
|
{
|
|
struct thread *td;
|
|
|
|
td = curthread;
|
|
critical_exit();
|
|
td->td_md.md_spinlock_count--;
|
|
if (td->td_md.md_spinlock_count == 0)
|
|
intr_restore(td->td_md.md_saved_msr);
|
|
}
|
|
|
|
/* Shutdown the CPU as much as possible. */
|
|
void
|
|
cpu_halt(void)
|
|
{
|
|
|
|
mtmsr(mfmsr() & ~(PSL_CE | PSL_EE | PSL_ME | PSL_DE));
|
|
while (1);
|
|
}
|
|
|
|
int
|
|
ptrace_set_pc(struct thread *td, unsigned long addr)
|
|
{
|
|
struct trapframe *tf;
|
|
|
|
tf = td->td_frame;
|
|
tf->srr0 = (register_t)addr;
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
ptrace_single_step(struct thread *td)
|
|
{
|
|
struct trapframe *tf;
|
|
|
|
tf = td->td_frame;
|
|
tf->srr1 |= PSL_DE;
|
|
tf->cpu.booke.dbcr0 |= (DBCR0_IDM | DBCR0_IC);
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
ptrace_clear_single_step(struct thread *td)
|
|
{
|
|
struct trapframe *tf;
|
|
|
|
tf = td->td_frame;
|
|
tf->srr1 &= ~PSL_DE;
|
|
tf->cpu.booke.dbcr0 &= ~(DBCR0_IDM | DBCR0_IC);
|
|
return (0);
|
|
}
|
|
|
|
void
|
|
kdb_cpu_clear_singlestep(void)
|
|
{
|
|
register_t r;
|
|
|
|
r = mfspr(SPR_DBCR0);
|
|
mtspr(SPR_DBCR0, r & ~DBCR0_IC);
|
|
kdb_frame->srr1 &= ~PSL_DE;
|
|
}
|
|
|
|
void
|
|
kdb_cpu_set_singlestep(void)
|
|
{
|
|
register_t r;
|
|
|
|
r = mfspr(SPR_DBCR0);
|
|
mtspr(SPR_DBCR0, r | DBCR0_IC | DBCR0_IDM);
|
|
kdb_frame->srr1 |= PSL_DE;
|
|
}
|
|
|
|
void
|
|
bzero(void *buf, size_t len)
|
|
{
|
|
caddr_t p;
|
|
|
|
p = buf;
|
|
|
|
while (((vm_offset_t) p & (sizeof(u_long) - 1)) && len) {
|
|
*p++ = 0;
|
|
len--;
|
|
}
|
|
|
|
while (len >= sizeof(u_long) * 8) {
|
|
*(u_long*) p = 0;
|
|
*((u_long*) p + 1) = 0;
|
|
*((u_long*) p + 2) = 0;
|
|
*((u_long*) p + 3) = 0;
|
|
len -= sizeof(u_long) * 8;
|
|
*((u_long*) p + 4) = 0;
|
|
*((u_long*) p + 5) = 0;
|
|
*((u_long*) p + 6) = 0;
|
|
*((u_long*) p + 7) = 0;
|
|
p += sizeof(u_long) * 8;
|
|
}
|
|
|
|
while (len >= sizeof(u_long)) {
|
|
*(u_long*) p = 0;
|
|
len -= sizeof(u_long);
|
|
p += sizeof(u_long);
|
|
}
|
|
|
|
while (len) {
|
|
*p++ = 0;
|
|
len--;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* XXX what is the better/proper place for this routine?
|
|
*/
|
|
int
|
|
mem_valid(vm_offset_t addr, int len)
|
|
{
|
|
|
|
return (1);
|
|
}
|