260 lines
9.3 KiB
C
260 lines
9.3 KiB
C
/*
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* Copyright (c) 1996, Sujal M. Patel
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Sujal M. Patel
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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* from: pnp.h,v 1.7 1998/09/13 22:15:44 eivind Exp
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*/
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#ifndef _ISA_PNPREG_H_
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#define _ISA_PNPREG_H_
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/* Maximum Number of PnP Devices. 8 should be plenty */
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#define PNP_MAX_CARDS 8
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#if 0
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/*
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* the following is the maximum number of PnP Logical devices that
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* userconfig can handle.
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*/
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#define MAX_PNP_LDN 20
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#endif
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/* Static ports to access PnP state machine */
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#if defined(PC98) && defined(KERNEL)
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/* pnp.h is included from pnpinfo.c. */
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#define _PNP_ADDRESS 0x259
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#define _PNP_WRITE_DATA 0xa59
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#else
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#define _PNP_ADDRESS 0x279
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#define _PNP_WRITE_DATA 0xa79
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#endif
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/* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */
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#define PNP_SET_RD_DATA 0x00
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/***
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Writing to this location modifies the address of the port used for
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reading from the Plug and Play ISA cards. Bits[7:0] become I/O
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read port address bits[9:2]. Reads from this register are ignored.
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***/
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#define PNP_SERIAL_ISOLATION 0x01
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/***
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A read to this register causes a Plug and Play cards in the Isolation
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state to compare one bit of the boards ID.
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This register is read only.
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***/
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#define PNP_CONFIG_CONTROL 0x02
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#define PNP_CONFIG_CONTROL_RESET_CSN 0x04
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#define PNP_CONFIG_CONTROL_WAIT_FOR_KEY 0x02
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#define PNP_CONFIG_CONTROL_RESET 0x01
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/***
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Bit[2] Reset CSN to 0
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Bit[1] Return to the Wait for Key state
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Bit[0] Reset all logical devices and restore configuration
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registers to their power-up values.
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A write to bit[0] of this register performs a reset function on
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all logical devices. This resets the contents of configuration
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registers to their default state. All card's logical devices
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enter their default state and the CSN is preserved.
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A write to bit[1] of this register causes all cards to enter the
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Wait for Key state but all CSNs are preserved and logical devices
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are not affected.
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A write to bit[2] of this register causes all cards to reset their
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CSN to zero .
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This register is write-only. The values are not sticky, that is,
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hardware will automatically clear them and there is no need for
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software to clear the bits.
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***/
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#define PNP_WAKE 0x03
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/***
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A write to this port will cause all cards that have a CSN that
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matches the write data[7:0] to go from the Sleep state to the either
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the Isolation state if the write data for this command is zero or
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the Config state if the write data is not zero. Additionally, the
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pointer to the byte-serial device is reset. This register is
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writeonly.
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***/
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#define PNP_RESOURCE_DATA 0x04
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/***
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A read from this address reads the next byte of resource information.
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The Status register must be polled until bit[0] is set before this
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register may be read. This register is read only.
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***/
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#define PNP_STATUS 0x05
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/***
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Bit[0] when set indicates it is okay to read the next data byte
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from the Resource Data register. This register is readonly.
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***/
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#define PNP_SET_CSN 0x06
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/***
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A write to this port sets a card's CSN. The CSN is a value uniquely
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assigned to each ISA card after the serial identification process
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so that each card may be individually selected during a Wake[CSN]
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command. This register is read/write.
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***/
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#define PNP_SET_LDN 0x07
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/***
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Selects the current logical device. All reads and writes of memory,
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I/O, interrupt and DMA configuration information access the registers
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of the logical device written here. In addition, the I/O Range
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Check and Activate commands operate only on the selected logical
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device. This register is read/write. If a card has only 1 logical
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device, this location should be a read-only value of 0x00.
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***/
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/*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/
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/*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/
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#define PNP_ACTIVATE 0x30
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/***
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For each logical device there is one activate register that controls
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whether or not the logical device is active on the ISA bus. Bit[0],
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if set, activates the logical device. Bits[7:1] are reserved and
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must return 0 on reads. This is a read/write register. Before a
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logical device is activated, I/O range check must be disabled.
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***/
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#define PNP_IO_RANGE_CHECK 0x31
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#define PNP_IO_RANGE_CHECK_ENABLE 0x02
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#define PNP_IO_RANGE_CHECK_READ_AS_55 0x01
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/***
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This register is used to perform a conflict check on the I/O port
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range programmed for use by a logical device.
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Bit[7:2] Reserved and must return 0 on reads
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Bit[1] Enable I/O Range check, if set then I/O Range Check
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is enabled. I/O range check is only valid when the logical
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device is inactive.
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Bit[0], if set, forces the logical device to respond to I/O reads
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of the logical device's assigned I/O range with a 0x55 when I/O
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range check is in operation. If clear, the logical device drives
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0xAA. This register is read/write.
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***/
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/*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/
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/*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/
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#define PNP_MEM_BASE_HIGH(i) (0x40 + 8*(i))
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#define PNP_MEM_BASE_LOW(i) (0x41 + 8*(i))
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#define PNP_MEM_CONTROL(i) (0x42 * 8*(i))
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#define PNP_MEM_CONTROL_16BIT 0x2
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#define PNP_MEM_CONTROL_LIMIT 0x1
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#define PNP_MEM_RANGE_HIGH(i) (0x43 + 8*(i))
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#define PNP_MEM_RANGE_LOW(i) (0x44 + 8*(i))
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/***
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Four memory resource registers per range, four ranges.
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Fill with 0 if no ranges are enabled.
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Offset 0: RW Memory base address bits[23:16]
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Offset 1: RW Memory base address bits[15:8]
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Offset 2: Memory control
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Bit[1] specifies 8/16-bit control. This bit is set to indicate
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16-bit memory, and cleared to indicate 8-bit memory.
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Bit[0], if cleared, indicates the next field can be used as a range
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length for decode (implies range length and base alignment of memory
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descriptor are equal).
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Bit[0], if set, indicates the next field is the upper limit for
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the address. - - Bit[0] is read-only.
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Offset 3: RW upper limit or range len, bits[23:16]
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Offset 4: RW upper limit or range len, bits[15:8]
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Offset 5-Offset 7: filler, unused.
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***/
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#define PNP_IO_BASE_HIGH(i) (0x60 + 2*(i))
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#define PNP_IO_BASE_LOW(i) (0x61 + 2*(i))
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/***
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Eight ranges, two bytes per range.
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Offset 0: I/O port base address bits[15:8]
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Offset 1: I/O port base address bits[7:0]
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***/
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#define PNP_IRQ_LEVEL(i) (0x70 + 2*(i))
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#define PNP_IRQ_TYPE(i) (0x71 + 2*(i))
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/***
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Two entries, two bytes per entry.
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Offset 0: RW interrupt level (1..15, 0=unused).
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Offset 1: Bit[1]: level(1:hi, 0:low),
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Bit[0]: type (1:level, 0:edge)
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byte 1 can be readonly if 1 type of int is used.
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***/
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#define PNP_DMA_CHANNEL(i) (0x74 + 1*(i))
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/***
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Two entries, one byte per entry. Bits[2:0] select
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which DMA channel is in use for DMA 0. Zero selects DMA channel
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0, seven selects DMA channel 7. DMA channel 4, the cascade channel
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is used to indicate no DMA channel is active.
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***/
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/*** 32-bit memory accesses are at 0x76 ***/
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/* Macros to parse Resource IDs */
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#define PNP_RES_TYPE(a) (a >> 7)
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#define PNP_SRES_NUM(a) (a >> 3)
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#define PNP_SRES_LEN(a) (a & 0x07)
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#define PNP_LRES_NUM(a) (a & 0x7f)
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/* Small Resource Item names */
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#define PNP_TAG_VERSION 0x1
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#define PNP_TAG_LOGICAL_DEVICE 0x2
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#define PNP_TAG_COMPAT_DEVICE 0x3
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#define PNP_TAG_IRQ_FORMAT 0x4
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#define PNP_TAG_DMA_FORMAT 0x5
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#define PNP_TAG_START_DEPENDANT 0x6
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#define PNP_TAG_END_DEPENDANT 0x7
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#define PNP_TAG_IO_RANGE 0x8
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#define PNP_TAG_IO_FIXED 0x9
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#define PNP_TAG_RESERVED 0xa-0xd
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#define PNP_TAG_VENDOR 0xe
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#define PNP_TAG_END 0xf
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/* Large Resource Item names */
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#define PNP_TAG_MEMORY_RANGE 0x1
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#define PNP_TAG_ID_ANSI 0x2
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#define PNP_TAG_ID_UNICODE 0x3
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#define PNP_TAG_LARGE_VENDOR 0x4
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#define PNP_TAG_MEMORY32_RANGE 0x5
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#define PNP_TAG_MEMORY32_FIXED 0x6
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#define PNP_TAG_LARGE_RESERVED 0x7-0x7f
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#endif /* !_ISA_PNPREG_H_ */
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