1537078d8f
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
228 lines
7.9 KiB
C
228 lines
7.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_highpoint_chipinit(device_t dev);
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static int ata_highpoint_ch_attach(device_t dev);
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static int ata_highpoint_setmode(device_t dev, int target, int mode);
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static int ata_highpoint_check_80pin(device_t dev, int mode);
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/* misc defines */
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#define HPT_366 0
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#define HPT_370 1
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#define HPT_372 2
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#define HPT_374 3
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#define HPT_OLD 1
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/*
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* HighPoint chipset support functions
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*/
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static int
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ata_highpoint_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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const struct ata_chip_id *idx;
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static const struct ata_chip_id ids[] =
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{{ ATA_HPT374, 0x07, HPT_374, 0, ATA_UDMA6, "HPT374" },
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{ ATA_HPT372, 0x02, HPT_372, 0, ATA_UDMA6, "HPT372N" },
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{ ATA_HPT372, 0x01, HPT_372, 0, ATA_UDMA6, "HPT372" },
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{ ATA_HPT371, 0x01, HPT_372, 0, ATA_UDMA6, "HPT371" },
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{ ATA_HPT366, 0x05, HPT_372, 0, ATA_UDMA6, "HPT372" },
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{ ATA_HPT366, 0x03, HPT_370, 0, ATA_UDMA5, "HPT370" },
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{ ATA_HPT366, 0x02, HPT_366, 0, ATA_UDMA4, "HPT368" },
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{ ATA_HPT366, 0x00, HPT_366, HPT_OLD, ATA_UDMA4, "HPT366" },
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{ ATA_HPT302, 0x01, HPT_372, 0, ATA_UDMA6, "HPT302" },
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{ 0, 0, 0, 0, 0, 0}};
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char buffer[64];
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if (pci_get_vendor(dev) != ATA_HIGHPOINT_ID)
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return ENXIO;
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if (!(idx = ata_match_chip(dev, ids)))
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return ENXIO;
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strcpy(buffer, "HighPoint ");
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strcat(buffer, idx->text);
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if (idx->cfg1 == HPT_374) {
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if (pci_get_function(dev) == 0)
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strcat(buffer, " (channel 0+1)");
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if (pci_get_function(dev) == 1)
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strcat(buffer, " (channel 2+3)");
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}
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sprintf(buffer, "%s %s controller", buffer, ata_mode2str(idx->max_dma));
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device_set_desc_copy(dev, buffer);
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ctlr->chip = idx;
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ctlr->chipinit = ata_highpoint_chipinit;
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return (BUS_PROBE_LOW_PRIORITY);
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}
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static int
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ata_highpoint_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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if (ctlr->chip->cfg2 == HPT_OLD) {
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/* disable interrupt prediction */
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pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x80), 1);
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}
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else {
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/* disable interrupt prediction */
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pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
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pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
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/* enable interrupts */
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pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x10), 1);
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/* set clocks etc */
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if (ctlr->chip->cfg1 < HPT_372)
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pci_write_config(dev, 0x5b, 0x22, 1);
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else
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pci_write_config(dev, 0x5b,
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(pci_read_config(dev, 0x5b, 1) & 0x01) | 0x20, 1);
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}
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ctlr->ch_attach = ata_highpoint_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->setmode = ata_highpoint_setmode;
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return 0;
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}
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static int
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ata_highpoint_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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/* setup the usual register normal pci style */
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if (ata_pci_ch_attach(dev))
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return (ENXIO);
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ch->flags |= ATA_ALWAYS_DMASTAT;
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ch->flags |= ATA_CHECKS_CABLE;
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if (ctlr->chip->cfg1 == HPT_366)
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ch->flags |= ATA_NO_ATAPI_DMA;
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return (0);
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}
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static int
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ata_highpoint_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int devno = (ch->unit << 1) + target;
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static const uint32_t timings33[][4] = {
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/* HPT366 HPT370 HPT372 HPT374 mode */
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{ 0x40d0a7aa, 0x06914e57, 0x0d029d5e, 0x0ac1f48a }, /* PIO 0 */
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{ 0x40d0a7a3, 0x06914e43, 0x0d029d26, 0x0ac1f465 }, /* PIO 1 */
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{ 0x40d0a753, 0x06514e33, 0x0c829ca6, 0x0a81f454 }, /* PIO 2 */
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{ 0x40c8a742, 0x06514e22, 0x0c829c84, 0x0a81f443 }, /* PIO 3 */
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{ 0x40c8a731, 0x06514e21, 0x0c829c62, 0x0a81f442 }, /* PIO 4 */
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{ 0x20c8a797, 0x26514e97, 0x2c82922e, 0x228082ea }, /* MWDMA 0 */
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{ 0x20c8a732, 0x26514e33, 0x2c829266, 0x22808254 }, /* MWDMA 1 */
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{ 0x20c8a731, 0x26514e21, 0x2c829262, 0x22808242 }, /* MWDMA 2 */
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{ 0x10c8a731, 0x16514e31, 0x1c829c62, 0x121882ea }, /* UDMA 0 */
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{ 0x10cba731, 0x164d4e31, 0x1c9a9c62, 0x12148254 }, /* UDMA 1 */
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{ 0x10caa731, 0x16494e31, 0x1c929c62, 0x120c8242 }, /* UDMA 2 */
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{ 0x10cfa731, 0x166d4e31, 0x1c8e9c62, 0x128c8242 }, /* UDMA 3 */
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{ 0x10c9a731, 0x16454e31, 0x1c8a9c62, 0x12ac8242 }, /* UDMA 4 */
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{ 0, 0x16454e31, 0x1c8a9c62, 0x12848242 }, /* UDMA 5 */
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{ 0, 0, 0x1c869c62, 0x12808242 } /* UDMA 6 */
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};
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mode = min(mode, ctlr->chip->max_dma);
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mode = ata_highpoint_check_80pin(dev, mode);
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/*
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* most if not all HPT chips cant really handle that the device is
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* running at ATA_UDMA6/ATA133 speed, so we cheat at set the device to
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* a max of ATA_UDMA5/ATA100 to guard against suboptimal performance
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*/
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mode = min(mode, ATA_UDMA5);
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pci_write_config(parent, 0x40 + (devno << 2),
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timings33[ata_mode2idx(mode)][ctlr->chip->cfg1], 4);
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return (mode);
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}
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static int
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ata_highpoint_check_80pin(device_t dev, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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u_int8_t reg, val, res;
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if (ctlr->chip->cfg1 == HPT_374 && pci_get_function(parent) == 1) {
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reg = ch->unit ? 0x57 : 0x53;
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val = pci_read_config(parent, reg, 1);
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pci_write_config(parent, reg, val | 0x80, 1);
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}
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else {
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reg = 0x5b;
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val = pci_read_config(parent, reg, 1);
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pci_write_config(parent, reg, val & 0xfe, 1);
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}
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res = pci_read_config(parent, 0x5a, 1) & (ch->unit ? 0x1:0x2);
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pci_write_config(parent, reg, val, 1);
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if (ata_dma_check_80pin && mode > ATA_UDMA2 && res) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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return mode;
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}
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ATA_DECLARE_DRIVER(ata_highpoint);
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