c6a3d2bb77
register mapping. I'm not sure whether it comes from the fact that controllers live behind certain PCI brdge(PLX PCI 6152 33BC) and the bridge has some issues in handling I/O space register mapping. Unfortunately it's not possible to narrow down to an exact controller that shows this issue because RealTek used the same PCI device/revision id again. In theory, it's possible to check parent PCI bridge device and change rl(4) to use memory space register mapping if the parent PCI bridge is PLX PCI 6152. But I didn't try to do that and we wouldn't get much benefit with added complexity. Blindly switching to use memory space register mapping for rl(4) may make most old controllers not to work. At least, I don't want to take potential risk from such change. So use I/O space register mapping by default but give users chance to override it via a tunable. The tunable to use memory space register mapping would be given by adding the following line to /boot/loader.conf file. dev.rl.%d.prefer_iomap="0" This change makes P811B quad-port work with this tunable. Tested by: Nikola Kalpazanov ( n.kalpazanov <> gmail dot com ) MFC after: 1 week |
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| .. | ||
| alpm.c | ||
| amdpm.c | ||
| amdsmb.c | ||
| if_rl.c | ||
| if_rlreg.h | ||
| intpm.c | ||
| intpmreg.h | ||
| locate.pl | ||
| ncr.c | ||
| ncrreg.h | ||
| nfsmb.c | ||
| viapm.c | ||