ad2a31513f
tree structure that encodes the level of cache sharing and other properties. - Provide several convenience functions for creating one and two level cpu trees as well as a default flat topology. The system now always has some topology. - On i386 and amd64 create a seperate level in the hierarchy for HTT and multi-core cpus. This will allow the scheduler to intelligently load balance non-uniform cores. Presently we don't detect what level of the cache hierarchy is shared at each level in the topology. - Add a mechanism for testing common topologies that have more information than the MD code is able to provide via the kern.smp.topology tunable. This should be considered a debugging tool only and not a stable api. Sponsored by: Nokia |
||
|---|---|---|
| .. | ||
| central | ||
| compile | ||
| conf | ||
| ebus | ||
| fhc | ||
| include | ||
| isa | ||
| pci | ||
| sbus | ||
| sparc64 | ||