181 lines
4.9 KiB
C
181 lines
4.9 KiB
C
/*-
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* Copyright (c) 2009 Yohanes Nugroho <yohanes@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM_ECONA_REG_H
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#define _ARM_ECONA_REG_H
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#define ECONA_SRAM_SIZE 0x10000000
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#define ECONA_DRAM_BASE 0x00000000 /* DRAM (via DDR Control Module) */
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#define ECONA_SDRAM_BASE 0x40000000
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#define ECONA_SDRAM_SIZE 0x1000000
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#define ECONA_IO_BASE 0x70000000
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#define ECONA_IO_SIZE 0x0E000000
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#define ECONA_PIC_BASE 0x0D000000
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#define ECONA_PIC_SIZE 0x01000000
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#define ECONA_UART_BASE 0x08000000
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#define ECONA_UART_SIZE 0x01000000
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#define ECONA_IRQ_UART 0xA
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#define ECONA_TIMER_BASE 0x09000000
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#define ECONA_TIMER_SIZE 0x01000000
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#define ECONA_IRQ_TIMER_1 0
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#define ECONA_IRQ_TIMER_2 1
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#define ECONA_IRQ_OHCI 23
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#define ECONA_IRQ_EHCI 24
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#define ECONA_NET_BASE 0x00000000
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#define ECONA_SYSTEM_BASE 0x07000000
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#define ECONA_SYSTEM_SIZE 0x01000000
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#define ECONA_NET_SIZE 0x01000000
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#define ECONA_CFI_PBASE 0x10000000
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#define ECONA_CFI_VBASE 0xD0000000
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#define ECONA_CFI_SIZE 0x10000000
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#define ECONA_IRQ_STATUS 18
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#define ECONA_IRQ_TSTC 19
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#define ECONA_IRQ_FSRC 20
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#define ECONA_IRQ_TSQE 21
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#define ECONA_IRQ_FSQF 22
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#define ECONA_IRQ_SYSTEM 0
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#define ECONA_EHCI_PBASE 0xC8000000
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#define ECONA_EHCI_VBASE 0xF8000000
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#define ECONA_EHCI_SIZE 0x8000000
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#define ECONA_OHCI_PBASE 0xC0000000
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#define ECONA_OHCI_VBASE 0xF0000000
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#define ECONA_OHCI_SIZE 0x8000000
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#define ECONA_USB_SIZE 0xf000000
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/*Interrupt controller*/
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#define INTC_LEVEL_TRIGGER 0
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#define INTC_EDGE_TRIGGER 1
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#define INTC_ACTIVE_HIGH 0
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#define INTC_ACTIVE_LOW 1
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/*
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* define rising/falling edge for edge trigger mode
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*/
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#define INTC_RISING_EDGE 0
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#define INTC_FALLING_EDGE 1
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#define INTC_INTERRUPT_SOURCE_REG_OFFSET 0x00
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#define INTC_INTERRUPT_MASK_REG_OFFSET 0x04
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#define INTC_INTERRUPT_CLEAR_EDGE_TRIGGER_REG_OFFSET 0x08
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#define INTC_INTERRUPT_TRIGGER_MODE_REG_OFFSET 0x0C
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#define INTC_INTERRUPT_TRIGGER_LEVEL_REG_OFFSET 0x10
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#define INTC_INTERRUPT_STATUS_REG_OFFSET 0x14
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#define INTC_FIQ_MODE_SELECT_REG_OFFSET 0x18
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#define INTC_SOFTWARE_INTERRUPT_REG_OFFSET 0x1C
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/*
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* define rising/falling edge for edge trigger mode
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*/
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#define INTC_RISING_EDGE 0
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#define INTC_FALLING_EDGE 1
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#define TIMER_TM1_COUNTER_REG 0x00
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#define TIMER_TM1_LOAD_REG 0x04
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#define TIMER_TM1_MATCH1_REG 0x08
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#define TIMER_TM1_MATCH2_REG 0x0C
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#define TIMER_TM2_COUNTER_REG 0x10
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#define TIMER_TM2_LOAD_REG 0x14
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#define TIMER_TM2_MATCH1_REG 0x18
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#define TIMER_TM2_MATCH2_REG 0x1C
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#define TIMER_TM_CR_REG 0x30
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#define TIMER_TM_INTR_STATUS_REG 0x34
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#define TIMER_TM_INTR_MASK_REG 0x38
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#define TIMER_TM_REVISION_REG 0x3C
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#define INTC_TIMER1_BIT_INDEX 0
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#define TIMER1_UP_DOWN_COUNT (1<<9)
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#define TIMER2_UP_DOWN_COUNT (1<<10)
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#define TIMER1_MATCH1_INTR (1<<0)
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#define TIMER1_MATCH2_INTR (1<<1)
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#define TIMER1_OVERFLOW_INTR (1<<2)
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#define TIMER2_MATCH1_INTR (1<<3)
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#define TIMER2_MATCH2_INTR (1<<4)
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#define TIMER2_OVERFLOW_INTR (1<<5)
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#define TIMER_CLOCK_SOURCE_PCLK 0
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#define TIMER_CLOCK_SOURCE_EXT_CLK 1
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/*
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* define interrupt trigger mode
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*/
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#define INTC_LEVEL_TRIGGER 0
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#define INTC_EDGE_TRIGGER 1
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#define INTC_TRIGGER_UNKNOWN -1
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#define TIMER1_OVERFLOW_INTERRUPT (1<<2)
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#define TIMER2_OVERFLOW_INTERRUPT (1<<5)
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#define TIMER_INTERRUPT_STATUS_REG 0x34
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#define TIMER1_ENABLE (1<<0)
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#define TIMER1_CLOCK_SOURCE (1<<1)
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#define TIMER1_OVERFLOW_ENABLE (1<<2)
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#define TIMER2_ENABLE (1<<3)
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#define TIMER2_CLOCK_SOURCE (1<<4)
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#define TIMER2_OVERFLOW_ENABLE (1<<5)
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#define TIMER_1 1
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#define EC_UART_CLOCK 14769200
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#define EC_UART_REGSHIFT 2
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#define SYSTEM_CLOCK 0x14
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#define RESET_CONTROL 0x4
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#define GLOBAL_RESET 0x1
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#define NET_INTERFACE_RESET (0x1 << 4)
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#endif
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