freebsd-skq/sys/riscv
Ruslan Bukin f2e299880a Release secondary cores from WFI (wait for interrupt) by sending them
an IPI.

This does not work however yet in QEMU. As a temporary workaround set
software interrupt pending bit manually on a local core to ensure WFI
doesn't halt the hart.

This is required to smpboot in QEMU.

Sponsored by:	DARPA, AFRL
2018-06-12 16:47:33 +00:00
..
conf Update several more URLs 2017-10-29 08:17:03 +00:00
include Export a breakpoint() function to userland for riscv. 2018-05-16 16:56:35 +00:00
riscv Release secondary cores from WFI (wait for interrupt) by sending them 2018-06-12 16:47:33 +00:00