551 lines
16 KiB
C
551 lines
16 KiB
C
/*-
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Sundance PCI device/vendor ID for the
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* ST201 chip.
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*/
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#define ST_VENDORID 0x13F0
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#define ST_DEVICEID_ST201_1 0x0200
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#define ST_DEVICEID_ST201_2 0x0201
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/*
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* D-Link PCI device/vendor ID for the DL10050[AB] chip
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*/
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#define DL_VENDORID 0x1186
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#define DL_DEVICEID_DL10050 0x1002
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/*
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* Register definitions for the Sundance Technologies ST201 PCI
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* fast ethernet controller. The register space is 128 bytes long and
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* can be accessed using either PCI I/O space or PCI memory mapping.
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* There are 32-bit, 16-bit and 8-bit registers.
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*/
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#define STE_DMACTL 0x00
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#define STE_TX_DMALIST_PTR 0x04
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#define STE_TX_DMABURST_THRESH 0x08
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#define STE_TX_DMAURG_THRESH 0x09
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#define STE_TX_DMAPOLL_PERIOD 0x0A
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#define STE_RX_DMASTATUS 0x0C
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#define STE_RX_DMALIST_PTR 0x10
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#define STE_RX_DMABURST_THRESH 0x14
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#define STE_RX_DMAURG_THRESH 0x15
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#define STE_RX_DMAPOLL_PERIOD 0x16
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#define STE_DEBUGCTL 0x1A
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#define STE_ASICCTL 0x30
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#define STE_EEPROM_DATA 0x34
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#define STE_EEPROM_CTL 0x36
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#define STE_FIFOCTL 0x3A
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#define STE_TX_STARTTHRESH 0x3C
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#define STE_RX_EARLYTHRESH 0x3E
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#define STE_EXT_ROMADDR 0x40
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#define STE_EXT_ROMDATA 0x44
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#define STE_WAKE_EVENT 0x45
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#define STE_TX_STATUS 0x46
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#define STE_TX_FRAMEID 0x47
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#define STE_COUNTDOWN 0x48
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#define STE_ISR_ACK 0x4A
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#define STE_IMR 0x4C
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#define STE_ISR 0x4E
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#define STE_MACCTL0 0x50
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#define STE_MACCTL1 0x52
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#define STE_PAR0 0x54
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#define STE_PAR1 0x56
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#define STE_PAR2 0x58
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#define STE_MAX_FRAMELEN 0x5A
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#define STE_RX_MODE 0x5C
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#define STE_TX_RECLAIM_THRESH 0x5D
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#define STE_PHYCTL 0x5E
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#define STE_MAR0 0x60
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#define STE_MAR1 0x62
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#define STE_MAR2 0x64
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#define STE_MAR3 0x66
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#define STE_STATS 0x68
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#define STE_LATE_COLLS 0x75
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#define STE_MULTI_COLLS 0x76
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#define STE_SINGLE_COLLS 0x77
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#define STE_DMACTL_RXDMA_STOPPED 0x00000001
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#define STE_DMACTL_TXDMA_CMPREQ 0x00000002
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#define STE_DMACTL_TXDMA_STOPPED 0x00000004
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#define STE_DMACTL_RXDMA_COMPLETE 0x00000008
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#define STE_DMACTL_TXDMA_COMPLETE 0x00000010
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#define STE_DMACTL_RXDMA_STALL 0x00000100
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#define STE_DMACTL_RXDMA_UNSTALL 0x00000200
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#define STE_DMACTL_TXDMA_STALL 0x00000400
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#define STE_DMACTL_TXDMA_UNSTALL 0x00000800
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#define STE_DMACTL_TXDMA_INPROG 0x00004000
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#define STE_DMACTL_DMA_HALTINPROG 0x00008000
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#define STE_DMACTL_RXEARLY_ENABLE 0x00020000
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#define STE_DMACTL_COUNTDOWN_SPEED 0x00040000
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#define STE_DMACTL_COUNTDOWN_MODE 0x00080000
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#define STE_DMACTL_MWI_DISABLE 0x00100000
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#define STE_DMACTL_RX_DISCARD_OFLOWS 0x00400000
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#define STE_DMACTL_COUNTDOWN_ENABLE 0x00800000
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#define STE_DMACTL_TARGET_ABORT 0x40000000
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#define STE_DMACTL_MASTER_ABORT 0x80000000
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/*
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* TX DMA burst thresh is the number of 32-byte blocks that
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* must be loaded into the TX Fifo before a TXDMA burst request
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* will be issued.
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*/
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#define STE_TXDMABURST_THRESH 0x1F
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/*
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* The number of 32-byte blocks in the TX FIFO falls below the
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* TX DMA urgent threshold, a TX DMA urgent request will be
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* generated.
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*/
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#define STE_TXDMAURG_THRESH 0x3F
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/*
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* Number of 320ns intervals between polls of the TXDMA next
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* descriptor pointer (if we're using polling mode).
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*/
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#define STE_TXDMA_POLL_PERIOD 0x7F
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#define STE_RX_DMASTATUS_FRAMELEN 0x00001FFF
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#define STE_RX_DMASTATUS_RXERR 0x00004000
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#define STE_RX_DMASTATUS_DMADONE 0x00008000
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#define STE_RX_DMASTATUS_FIFO_OFLOW 0x00010000
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#define STE_RX_DMASTATUS_RUNT 0x00020000
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#define STE_RX_DMASTATUS_ALIGNERR 0x00040000
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#define STE_RX_DMASTATUS_CRCERR 0x00080000
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#define STE_RX_DMASTATUS_GIANT 0x00100000
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#define STE_RX_DMASTATUS_DRIBBLE 0x00800000
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#define STE_RX_DMASTATUS_DMA_OFLOW 0x01000000
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/*
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* RX DMA burst thresh is the number of 32-byte blocks that
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* must be present in the RX FIFO before a RXDMA bus master
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* request will be issued.
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*/
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#define STE_RXDMABURST_THRESH 0xFF
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/*
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* The number of 32-byte blocks in the RX FIFO falls below the
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* RX DMA urgent threshold, a RX DMA urgent request will be
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* generated.
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*/
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#define STE_RXDMAURG_THRESH 0x1F
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/*
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* Number of 320ns intervals between polls of the RXDMA complete
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* bit in the status field on the current RX descriptor (if we're
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* using polling mode).
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*/
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#define STE_RXDMA_POLL_PERIOD 0x7F
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#define STE_DEBUGCTL_GPIO0_CTL 0x0001
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#define STE_DEBUGCTL_GPIO1_CTL 0x0002
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#define STE_DEBUGCTL_GPIO0_DATA 0x0004
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#define STE_DEBUGCTL_GPIO1_DATA 0x0008
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#define STE_ASICCTL_ROMSIZE 0x00000002
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#define STE_ASICCTL_TX_LARGEPKTS 0x00000004
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#define STE_ASICCTL_RX_LARGEPKTS 0x00000008
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#define STE_ASICCTL_EXTROM_DISABLE 0x00000010
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#define STE_ASICCTL_PHYSPEED_10 0x00000020
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#define STE_ASICCTL_PHYSPEED_100 0x00000040
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#define STE_ASICCTL_PHYMEDIA 0x00000080
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#define STE_ASICCTL_FORCEDCONFIG 0x00000700
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#define STE_ASICCTL_D3RESET_DISABLE 0x00000800
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#define STE_ASICCTL_SPEEDUPMODE 0x00002000
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#define STE_ASICCTL_LEDMODE 0x00004000
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#define STE_ASICCTL_RSTOUT_POLARITY 0x00008000
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#define STE_ASICCTL_GLOBAL_RESET 0x00010000
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#define STE_ASICCTL_RX_RESET 0x00020000
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#define STE_ASICCTL_TX_RESET 0x00040000
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#define STE_ASICCTL_DMA_RESET 0x00080000
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#define STE_ASICCTL_FIFO_RESET 0x00100000
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#define STE_ASICCTL_NETWORK_RESET 0x00200000
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#define STE_ASICCTL_HOST_RESET 0x00400000
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#define STE_ASICCTL_AUTOINIT_RESET 0x00800000
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#define STE_ASICCTL_EXTRESET_RESET 0x01000000
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#define STE_ASICCTL_SOFTINTR 0x02000000
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#define STE_ASICCTL_RESET_BUSY 0x04000000
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#define STE_ASICCTL1_GLOBAL_RESET 0x0001
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#define STE_ASICCTL1_RX_RESET 0x0002
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#define STE_ASICCTL1_TX_RESET 0x0004
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#define STE_ASICCTL1_DMA_RESET 0x0008
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#define STE_ASICCTL1_FIFO_RESET 0x0010
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#define STE_ASICCTL1_NETWORK_RESET 0x0020
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#define STE_ASICCTL1_HOST_RESET 0x0040
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#define STE_ASICCTL1_AUTOINIT_RESET 0x0080
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#define STE_ASICCTL1_EXTRESET_RESET 0x0100
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#define STE_ASICCTL1_SOFTINTR 0x0200
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#define STE_ASICCTL1_RESET_BUSY 0x0400
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#define STE_EECTL_ADDR 0x00FF
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#define STE_EECTL_OPCODE 0x0300
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#define STE_EECTL_BUSY 0x1000
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#define STE_EEOPCODE_WRITE 0x0100
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#define STE_EEOPCODE_READ 0x0200
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#define STE_EEOPCODE_ERASE 0x0300
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#define STE_FIFOCTL_RAMTESTMODE 0x0001
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#define STE_FIFOCTL_OVERRUNMODE 0x0200
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#define STE_FIFOCTL_RXFIFOFULL 0x0800
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#define STE_FIFOCTL_TX_BUSY 0x4000
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#define STE_FIFOCTL_RX_BUSY 0x8000
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/*
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* The number of bytes that must in present in the TX FIFO before
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* transmission begins. Value should be in increments of 4 bytes.
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*/
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#define STE_TXSTART_THRESH 0x1FFC
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/*
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* Number of bytes that must be present in the RX FIFO before
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* an RX EARLY interrupt is generated.
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*/
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#define STE_RXEARLY_THRESH 0x1FFC
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#define STE_WAKEEVENT_WAKEPKT_ENB 0x01
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#define STE_WAKEEVENT_MAGICPKT_ENB 0x02
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#define STE_WAKEEVENT_LINKEVT_ENB 0x04
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#define STE_WAKEEVENT_WAKEPOLARITY 0x08
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#define STE_WAKEEVENT_WAKEPKTEVENT 0x10
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#define STE_WAKEEVENT_MAGICPKTEVENT 0x20
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#define STE_WAKEEVENT_LINKEVENT 0x40
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#define STE_WAKEEVENT_WAKEONLAN_ENB 0x80
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#define STE_TXSTATUS_RECLAIMERR 0x02
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#define STE_TXSTATUS_STATSOFLOW 0x04
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#define STE_TXSTATUS_EXCESSCOLLS 0x08
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#define STE_TXSTATUS_UNDERRUN 0x10
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#define STE_TXSTATUS_TXINTR_REQ 0x40
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#define STE_TXSTATUS_TXDONE 0x80
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#define STE_ISRACK_INTLATCH 0x0001
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#define STE_ISRACK_HOSTERR 0x0002
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#define STE_ISRACK_TX_DONE 0x0004
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#define STE_ISRACK_MACCTL_FRAME 0x0008
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#define STE_ISRACK_RX_DONE 0x0010
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#define STE_ISRACK_RX_EARLY 0x0020
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#define STE_ISRACK_SOFTINTR 0x0040
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#define STE_ISRACK_STATS_OFLOW 0x0080
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#define STE_ISRACK_LINKEVENT 0x0100
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#define STE_ISRACK_TX_DMADONE 0x0200
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#define STE_ISRACK_RX_DMADONE 0x0400
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#define STE_IMR_HOSTERR 0x0002
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#define STE_IMR_TX_DONE 0x0004
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#define STE_IMR_MACCTL_FRAME 0x0008
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#define STE_IMR_RX_DONE 0x0010
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#define STE_IMR_RX_EARLY 0x0020
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#define STE_IMR_SOFTINTR 0x0040
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#define STE_IMR_STATS_OFLOW 0x0080
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#define STE_IMR_LINKEVENT 0x0100
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#define STE_IMR_TX_DMADONE 0x0200
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#define STE_IMR_RX_DMADONE 0x0400
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#define STE_INTRS \
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(STE_IMR_RX_DMADONE|STE_IMR_TX_DMADONE| \
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STE_IMR_TX_DONE|STE_IMR_HOSTERR| \
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STE_IMR_LINKEVENT)
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#define STE_ISR_INTLATCH 0x0001
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#define STE_ISR_HOSTERR 0x0002
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#define STE_ISR_TX_DONE 0x0004
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#define STE_ISR_MACCTL_FRAME 0x0008
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#define STE_ISR_RX_DONE 0x0010
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#define STE_ISR_RX_EARLY 0x0020
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#define STE_ISR_SOFTINTR 0x0040
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#define STE_ISR_STATS_OFLOW 0x0080
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#define STE_ISR_LINKEVENT 0x0100
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#define STE_ISR_TX_DMADONE 0x0200
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#define STE_ISR_RX_DMADONE 0x0400
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/*
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* Note: the Sundance manual gives the impression that the's
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* only one 32-bit MACCTL register. In fact, there are two
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* 16-bit registers side by side, and you have to access them
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* separately.
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*/
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#define STE_MACCTL0_IPG 0x0003
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#define STE_MACCTL0_FULLDUPLEX 0x0020
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#define STE_MACCTL0_RX_GIANTS 0x0040
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#define STE_MACCTL0_FLOWCTL_ENABLE 0x0100
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#define STE_MACCTL0_RX_FCS 0x0200
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#define STE_MACCTL0_FIFOLOOPBK 0x0400
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#define STE_MACCTL0_MACLOOPBK 0x0800
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#define STE_MACCTL1_COLLDETECT 0x0001
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#define STE_MACCTL1_CARRSENSE 0x0002
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#define STE_MACCTL1_TX_BUSY 0x0004
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#define STE_MACCTL1_TX_ERROR 0x0008
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#define STE_MACCTL1_STATS_ENABLE 0x0020
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#define STE_MACCTL1_STATS_DISABLE 0x0040
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#define STE_MACCTL1_STATS_ENABLED 0x0080
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#define STE_MACCTL1_TX_ENABLE 0x0100
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#define STE_MACCTL1_TX_DISABLE 0x0200
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#define STE_MACCTL1_TX_ENABLED 0x0400
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#define STE_MACCTL1_RX_ENABLE 0x0800
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#define STE_MACCTL1_RX_DISABLE 0x1000
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#define STE_MACCTL1_RX_ENABLED 0x2000
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#define STE_MACCTL1_PAUSED 0x4000
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#define STE_IPG_96BT 0x00000000
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#define STE_IPG_128BT 0x00000001
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#define STE_IPG_224BT 0x00000002
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#define STE_IPG_544BT 0x00000003
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#define STE_RXMODE_UNICAST 0x01
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#define STE_RXMODE_ALLMULTI 0x02
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#define STE_RXMODE_BROADCAST 0x04
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#define STE_RXMODE_PROMISC 0x08
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#define STE_RXMODE_MULTIHASH 0x10
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#define STE_RXMODE_ALLIPMULTI 0x20
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#define STE_PHYCTL_MCLK 0x01
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#define STE_PHYCTL_MDATA 0x02
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#define STE_PHYCTL_MDIR 0x04
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#define STE_PHYCTL_CLK25_DISABLE 0x08
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#define STE_PHYCTL_DUPLEXPOLARITY 0x10
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#define STE_PHYCTL_DUPLEXSTAT 0x20
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#define STE_PHYCTL_SPEEDSTAT 0x40
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#define STE_PHYCTL_LINKSTAT 0x80
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/*
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* EEPROM offsets.
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*/
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#define STE_EEADDR_CONFIGPARM 0x00
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#define STE_EEADDR_ASICCTL 0x02
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#define STE_EEADDR_SUBSYS_ID 0x04
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#define STE_EEADDR_SUBVEN_ID 0x08
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#define STE_EEADDR_NODE0 0x10
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#define STE_EEADDR_NODE1 0x12
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#define STE_EEADDR_NODE2 0x14
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/* PCI registers */
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#define STE_PCI_VENDOR_ID 0x00
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#define STE_PCI_DEVICE_ID 0x02
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#define STE_PCI_COMMAND 0x04
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#define STE_PCI_STATUS 0x06
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#define STE_PCI_CLASSCODE 0x09
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#define STE_PCI_LATENCY_TIMER 0x0D
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#define STE_PCI_HEADER_TYPE 0x0E
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#define STE_PCI_LOIO 0x10
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#define STE_PCI_LOMEM 0x14
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#define STE_PCI_BIOSROM 0x30
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#define STE_PCI_INTLINE 0x3C
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#define STE_PCI_INTPIN 0x3D
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#define STE_PCI_MINGNT 0x3E
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#define STE_PCI_MINLAT 0x0F
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#define STE_PCI_CAPID 0x50 /* 8 bits */
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#define STE_PCI_NEXTPTR 0x51 /* 8 bits */
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#define STE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
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#define STE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
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#define STE_PSTATE_MASK 0x0003
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#define STE_PSTATE_D0 0x0000
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#define STE_PSTATE_D1 0x0002
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#define STE_PSTATE_D2 0x0002
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#define STE_PSTATE_D3 0x0003
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#define STE_PME_EN 0x0010
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#define STE_PME_STATUS 0x8000
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struct ste_stats {
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u_int32_t ste_rx_bytes;
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u_int32_t ste_tx_bytes;
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u_int16_t ste_tx_frames;
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u_int16_t ste_rx_frames;
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u_int8_t ste_carrsense_errs;
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u_int8_t ste_late_colls;
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u_int8_t ste_multi_colls;
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u_int8_t ste_single_colls;
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u_int8_t ste_tx_frames_defered;
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u_int8_t ste_rx_lost_frames;
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u_int8_t ste_tx_excess_defers;
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u_int8_t ste_tx_abort_excess_colls;
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u_int8_t ste_tx_bcast_frames;
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u_int8_t ste_rx_bcast_frames;
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u_int8_t ste_tx_mcast_frames;
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u_int8_t ste_rx_mcast_frames;
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};
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struct ste_frag {
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u_int32_t ste_addr;
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u_int32_t ste_len;
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};
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#define STE_FRAG_LAST 0x80000000
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#define STE_FRAG_LEN 0x00001FFF
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#define STE_MAXFRAGS 8
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struct ste_desc {
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u_int32_t ste_next;
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u_int32_t ste_ctl;
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struct ste_frag ste_frags[STE_MAXFRAGS];
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};
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struct ste_desc_onefrag {
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u_int32_t ste_next;
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u_int32_t ste_status;
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struct ste_frag ste_frag;
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};
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#define STE_TXCTL_WORDALIGN 0x00000003
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#define STE_TXCTL_FRAMEID 0x000003FC
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#define STE_TXCTL_NOCRC 0x00002000
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#define STE_TXCTL_TXINTR 0x00008000
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#define STE_TXCTL_DMADONE 0x00010000
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#define STE_TXCTL_DMAINTR 0x80000000
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#define STE_RXSTAT_FRAMELEN 0x00001FFF
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#define STE_RXSTAT_FRAME_ERR 0x00004000
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#define STE_RXSTAT_DMADONE 0x00008000
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#define STE_RXSTAT_FIFO_OFLOW 0x00010000
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#define STE_RXSTAT_RUNT 0x00020000
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#define STE_RXSTAT_ALIGNERR 0x00040000
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#define STE_RXSTAT_CRCERR 0x00080000
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#define STE_RXSTAT_GIANT 0x00100000
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#define STE_RXSTAT_DRIBBLEBITS 0x00800000
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#define STE_RXSTAT_DMA_OFLOW 0x01000000
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#define STE_RXATAT_ONEBUF 0x10000000
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/*
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* register space access macros
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*/
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#define CSR_WRITE_4(sc, reg, val) \
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bus_space_write_4(sc->ste_btag, sc->ste_bhandle, reg, val)
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#define CSR_WRITE_2(sc, reg, val) \
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bus_space_write_2(sc->ste_btag, sc->ste_bhandle, reg, val)
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#define CSR_WRITE_1(sc, reg, val) \
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bus_space_write_1(sc->ste_btag, sc->ste_bhandle, reg, val)
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#define CSR_READ_4(sc, reg) \
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bus_space_read_4(sc->ste_btag, sc->ste_bhandle, reg)
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#define CSR_READ_2(sc, reg) \
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bus_space_read_2(sc->ste_btag, sc->ste_bhandle, reg)
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#define CSR_READ_1(sc, reg) \
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bus_space_read_1(sc->ste_btag, sc->ste_bhandle, reg)
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#define STE_TIMEOUT 1000
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#define STE_MIN_FRAMELEN 60
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#define STE_PACKET_SIZE 1536
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#define ETHER_ALIGN 2
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#define STE_RX_LIST_CNT 64
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#define STE_TX_LIST_CNT 128
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#define STE_INC(x, y) (x) = (x + 1) % y
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#define STE_NEXT(x, y) (x + 1) % y
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struct ste_type {
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u_int16_t ste_vid;
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u_int16_t ste_did;
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char *ste_name;
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};
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struct ste_list_data {
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struct ste_desc_onefrag ste_rx_list[STE_RX_LIST_CNT];
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struct ste_desc ste_tx_list[STE_TX_LIST_CNT];
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};
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struct ste_chain {
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struct ste_desc *ste_ptr;
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struct mbuf *ste_mbuf;
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struct ste_chain *ste_next;
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u_int32_t ste_phys;
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};
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struct ste_chain_onefrag {
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struct ste_desc_onefrag *ste_ptr;
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struct mbuf *ste_mbuf;
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struct ste_chain_onefrag *ste_next;
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};
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struct ste_chain_data {
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struct ste_chain_onefrag ste_rx_chain[STE_RX_LIST_CNT];
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struct ste_chain ste_tx_chain[STE_TX_LIST_CNT];
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struct ste_chain_onefrag *ste_rx_head;
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int ste_tx_prod;
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int ste_tx_cons;
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};
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struct ste_softc {
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struct ifnet *ste_ifp;
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bus_space_tag_t ste_btag;
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bus_space_handle_t ste_bhandle;
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struct resource *ste_res;
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struct resource *ste_irq;
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void *ste_intrhand;
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struct ste_type *ste_info;
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device_t ste_miibus;
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device_t ste_dev;
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int ste_tx_thresh;
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u_int8_t ste_link;
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int ste_if_flags;
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struct ste_chain *ste_tx_prev;
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struct ste_list_data *ste_ldata;
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struct ste_chain_data ste_cdata;
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struct callout ste_stat_callout;
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struct mtx ste_mtx;
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u_int8_t ste_one_phy;
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#ifdef DEVICE_POLLING
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int rxcycles;
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#endif
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};
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#define STE_LOCK(_sc) mtx_lock(&(_sc)->ste_mtx)
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#define STE_UNLOCK(_sc) mtx_unlock(&(_sc)->ste_mtx)
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#define STE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->ste_mtx, MA_OWNED)
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struct ste_mii_frame {
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u_int8_t mii_stdelim;
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u_int8_t mii_opcode;
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u_int8_t mii_phyaddr;
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u_int8_t mii_regaddr;
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u_int8_t mii_turnaround;
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u_int16_t mii_data;
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};
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/*
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* MII constants
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*/
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#define STE_MII_STARTDELIM 0x01
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#define STE_MII_READOP 0x02
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#define STE_MII_WRITEOP 0x01
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#define STE_MII_TURNAROUND 0x02
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