f26c810514
than one unit with four busses attached to it. This allows us to use existing fdt data which describes separate devices with separate resources. It also allows any combination of the units to be en/disabled in the board dts files. Adjust our dts code to match what's used by linux and u-boot now that we're structured to do so. Document lots of interesting stuff learned whiling doing this with a big comment block in the driver, so I don't have to re-learn it for the next round of changes.
623 lines
16 KiB
Plaintext
623 lines
16 KiB
Plaintext
/*
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* Copyright (c) 2012 The FreeBSD Foundation
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* All rights reserved.
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*
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* This software was developed by Semihalf under sponsorship from
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* the FreeBSD Foundation.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* Freescale i.MX515 Device Tree Source.
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*
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* $FreeBSD$
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*/
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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soc = &SOC;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "ARM,MCIMX515";
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reg = <0x0>;
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d-cache-line-size = <32>;
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i-cache-line-size = <32>;
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d-cache-size = <0x8000>;
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i-cache-size = <0x8000>;
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/* TODO: describe L2 cache also */
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timebase-frequency = <0>;
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bus-frequency = <0>;
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clock-frequency = <0>;
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};
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};
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localbus@e0000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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/* This reflects CPU decode windows setup. */
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ranges;
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tzic: tz-interrupt-controller@e0000000 {
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compatible = "fsl,imx51-tzic", "fsl,tzic";
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interrupt-controller;
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#interrupt-cells = <1>;
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reg = <0xe0000000 0x00004000>;
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};
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/*
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* 60000000 60000FFF 4K Debug ROM
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* 60001000 60001FFF 4K ETB
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* 60002000 60002FFF 4K ETM
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* 60003000 60003FFF 4K TPIU
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* 60004000 60004FFF 4K CTI0
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* 60005000 60005FFF 4K CTI1
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* 60006000 60006FFF 4K CTI2
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* 60007000 60007FFF 4K CTI3
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* 60008000 60008FFF 4K Cortex Debug Unit
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*
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* E0000000 E0003FFF 0x4000 TZIC
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*/
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};
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SOC: soc@70000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&tzic>;
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ranges = <0x70000000 0x70000000 0x14000000>;
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aips@70000000 { /* AIPS1 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&tzic>;
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ranges;
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/* Required by many devices, so better to stay first */
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/* 73FD4000 0x4000 CCM */
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clock@73fd4000 {
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compatible = "fsl,imx51-ccm";
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/* 83F80000 0x4000 DPLLIP1 */
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/* 83F84000 0x4000 DPLLIP2 */
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/* 83F88000 0x4000 DPLLIP3 */
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reg = <0x73fd4000 0x4000
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0x83F80000 0x4000
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0x83F84000 0x4000
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0x83F88000 0x4000>;
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interrupt-parent = <&tzic>;
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interrupts = <71 72>;
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status = "disabled";
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};
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/*
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* GPIO modules moved up - to have it attached for
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* drivers which rely on GPIO
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*/
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/* 73F84000 0x4000 GPIO1 */
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gpio1: gpio@73f84000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f84000 0x4000>;
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interrupt-parent = <&tzic>;
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interrupts = <50 51 42 43 44 45 46 47 48 49>;
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/* TODO: use <> also */
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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/* 73F88000 0x4000 GPIO2 */
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gpio2: gpio@73f88000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f88000 0x4000>;
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interrupt-parent = <&tzic>;
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interrupts = <52 53>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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/* 73F8C000 0x4000 GPIO3 */
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gpio3: gpio@73f8c000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f8c000 0x4000>;
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interrupt-parent = <&tzic>;
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interrupts = <54 55>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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/* 73F90000 0x4000 GPIO4 */
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gpio4: gpio@73f90000 {
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compatible = "fsl,imx51-gpio", "fsl,imx31-gpio";
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reg = <0x73f90000 0x4000>;
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interrupt-parent = <&tzic>;
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interrupts = <56 57>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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spba@70000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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interrupt-parent = <&tzic>;
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ranges;
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/* 70004000 0x4000 ESDHC 1 */
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esdhc@70004000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70004000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <1>;
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status = "disabled";
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};
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/* 70008000 0x4000 ESDHC 2 */
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esdhc@70008000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70008000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <2>;
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status = "disabled";
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};
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/* 7000C000 0x4000 UART 3 */
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uart3: serial@7000c000 {
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compatible = "fsl,imx51-uart", "fsl,imx-uart";
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reg = <0x7000c000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <33>;
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status = "disabled";
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};
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/* 70010000 0x4000 eCSPI1 */
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ecspi@70010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx51-ecspi";
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reg = <0x70010000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <36>;
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status = "disabled";
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};
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/* 70014000 0x4000 SSI2 irq30 */
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SSI2: ssi@70014000 {
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compatible = "fsl,imx51-ssi";
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reg = <0x70014000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <30>;
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status = "disabled";
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};
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/* 70020000 0x4000 ESDHC 3 */
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esdhc@70020000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70020000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <3>;
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status = "disabled";
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};
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/* 70024000 0x4000 ESDHC 4 */
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esdhc@70024000 {
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compatible = "fsl,imx51-esdhc";
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reg = <0x70024000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <4>;
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status = "disabled";
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};
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/* 70028000 0x4000 SPDIF */
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/* 91 SPDIF */
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/* 70030000 0x4000 PATA (PORT UDMA) irq70 */
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/* 70034000 0x4000 SLM */
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/* 70038000 0x4000 HSI2C */ /* 64 HS-I2C */
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/* 7003C000 0x4000 SPBA */
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};
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usbphy0: usbphy@0 {
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compatible = "usb-nop-xceiv";
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status = "okay";
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};
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usbotg: usb@73f80000 {
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compatible = "fsl,imx51-usb", "fsl,imx27-usb";
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reg = <0x73f80000 0x0200>;
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interrupts = <18>;
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fsl,usbmisc = <&usbmisc 0>;
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fsl,usbphy = <&usbphy0>;
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status = "disabled";
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};
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usbh1: usb@73f80200 {
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compatible = "fsl,imx51-usb", "fsl,imx27-usb";
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reg = <0x73f80200 0x0200>;
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interrupts = <14>;
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fsl,usbmisc = <&usbmisc 1>;
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status = "disabled";
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};
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usbh2: usb@73f80400 {
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compatible = "fsl,imx51-usb", "fsl,imx27-usb";
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reg = <0x73f80400 0x0200>;
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interrupts = <16>;
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fsl,usbmisc = <&usbmisc 2>;
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status = "disabled";
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};
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usbh3: usb@73f80600 {
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compatible = "fsl,imx51-usb", "fsl,imx27-usb";
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reg = <0x73f80600 0x0200>;
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interrupts = <17>;
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fsl,usbmisc = <&usbmisc 3>;
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status = "disabled";
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};
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usbmisc: usbmisc@73f80800 {
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#index-cells = <1>;
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compatible = "fsl,imx51-usbmisc";
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reg = <0x73f80800 0x200>;
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};
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/* 73F98000 0x4000 WDOG1 */
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wdog@73f98000 {
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f98000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <58>;
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status = "disabled";
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};
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/* 73F9C000 0x4000 WDOG2 (TZ) */
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wdog@73f9c000 {
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compatible = "fsl,imx51-wdt", "fsl,imx21-wdt";
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reg = <0x73f9c000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <59>;
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status = "disabled";
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};
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/* 73F94000 0x4000 KPP */
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keyboard@73f94000 {
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compatible = "fsl,imx51-kpp";
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reg = <0x73f94000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <60>;
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status = "disabled";
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};
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/* 73FA0000 0x4000 GPT */
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timer@73fa0000 {
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compatible = "fsl,imx51-gpt";
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reg = <0x73fa0000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <39>;
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status = "disabled";
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};
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/* 73FA4000 0x4000 SRTC */
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rtc@73fa4000 {
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compatible = "fsl,imx51-srtc";
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reg = <0x73fa4000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <24 25>;
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status = "disabled";
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};
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/* 73FA8000 0x4000 IOMUXC */
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iomux@73fa8000 {
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compatible = "fsl,imx51-iomux";
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reg = <0x73fa8000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <7>;
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};
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/* 73FAC000 0x4000 EPIT1 */
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epit1: timer@73fac000 {
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compatible = "fsl,imx51-epit";
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reg = <0x73fac000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <40>;
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status = "disabled";
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};
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/* 73FB0000 0x4000 EPIT2 */
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epit2: timer@73fb0000 {
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compatible = "fsl,imx51-epit";
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reg = <0x73fb0000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <41>;
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status = "disabled";
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};
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/* 73FB4000 0x4000 PWM1 */
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pwm@73fb4000 {
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compatible = "fsl,imx51-pwm";
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reg = <0x73fb4000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <61>;
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status = "disabled";
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};
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/* 73FB8000 0x4000 PWM2 */
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pwm@73fb8000 {
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compatible = "fsl,imx51-pwm";
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reg = <0x73fb8000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <94>;
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status = "disabled";
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};
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/* 73FBC000 0x4000 UART 1 */
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uart1: serial@73fbc000 {
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compatible = "fsl,imx51-uart", "fsl,imx-uart";
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reg = <0x73fbc000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <31>;
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status = "disabled";
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};
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/* 73FC0000 0x4000 UART 2 */
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uart2: serial@73fc0000 {
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compatible = "fsl,imx51-uart", "fsl,imx-uart";
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reg = <0x73fc0000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <32>;
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status = "disabled";
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};
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/* 73FC4000 0x4000 USBOH3 */
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/* NOTYET
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usb@73fc4000 {
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compatible = "fsl,imx51-otg";
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reg = <0x73fc4000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <>;
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status = "disabled";
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};
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*/
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/* 73FD0000 0x4000 SRC */
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reset@73fd0000 {
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compatible = "fsl,imx51-src";
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reg = <0x73fd0000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <75>;
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status = "disabled";
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};
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/* 73FD8000 0x4000 GPC */
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power@73fd8000 {
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compatible = "fsl,imx51-gpc";
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reg = <0x73fd8000 0x4000>;
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interrupt-parent = <&tzic>; interrupts = <73 74>;
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status = "disabled";
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};
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};
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aips@80000000 { /* AIPS2 */
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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|
#size-cells = <1>;
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interrupt-parent = <&tzic>;
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ranges;
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|
/* 83F94000 0x4000 AHBMAX */
|
|
/* 83F98000 0x4000 IIM */
|
|
/*
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* 69 IIM Interrupt request to the processor.
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|
* Indicates to the processor that program or
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|
* explicit.
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|
*/
|
|
/* 83F9C000 0x4000 CSU */
|
|
/*
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|
* 27 CSU Interrupt Request 1. Indicates to the
|
|
* processor that one or more alarm inputs were.
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|
*/
|
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|
|
/* 83FA0000 0x4000 TIGERP_PLATFORM_NE_32K_256K */
|
|
/* irq76 Neon Monitor Interrupt */
|
|
/* irq77 Performance Unit Interrupt */
|
|
/* irq78 CTI IRQ */
|
|
/* irq79 Debug Interrupt, Cross-Trigger Interface 1 */
|
|
/* irq80 Debug Interrupt, Cross-Trigger Interface 1 */
|
|
/* irq89 Debug Interrupt, Cross-Trigger Interface 2 */
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|
/* irq98 Debug Interrupt, Cross-Trigger Interface 3 */
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|
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|
/* 83FA4000 0x4000 OWIRE irq88 */
|
|
/* 83FA8000 0x4000 FIRI irq93 */
|
|
/* 83FAC000 0x4000 eCSPI2 */
|
|
ecspi@83fac000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-ecspi";
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|
reg = <0x83fac000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <37>;
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|
status = "disabled";
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|
};
|
|
|
|
/* 83FB0000 0x4000 SDMA */
|
|
sdma@83fb0000 {
|
|
compatible = "fsl,imx51-sdma", "fsl,imx35-sdma";
|
|
reg = <0x83fb0000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <6>;
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|
};
|
|
|
|
/* 83FB4000 0x4000 SCC */
|
|
/* 21 SCC Security Monitor High Priority Interrupt. */
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|
/* 22 SCC Secure (TrustZone) Interrupt. */
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|
/* 23 SCC Regular (Non-Secure) Interrupt. */
|
|
|
|
/* 83FB8000 0x4000 ROMCP */
|
|
/* 83FBC000 0x4000 RTIC */
|
|
/*
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|
* 26 RTIC RTIC (Trust Zone) Interrupt Request.
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|
* Indicates that the RTIC has completed hashing the
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|
*/
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|
|
|
/* 83FC0000 0x4000 CSPI */
|
|
cspi@83fc0000 {
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|
#address-cells = <1>;
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|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-cspi", "fsl,imx35-cspi";
|
|
reg = <0x83fc0000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <38>;
|
|
status = "disabled";
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|
};
|
|
|
|
/* 83FC4000 0x4000 I2C2 */
|
|
i2c@83fc4000 {
|
|
#address-cells = <1>;
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|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
|
|
reg = <0x83fc4000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <63>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 83FC8000 0x4000 I2C1 */
|
|
i2c@83fc8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx51-i2c", "fsl,imx1-i2c", "fsl,imx-i2c";
|
|
reg = <0x83fc8000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <62>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 83FCC000 0x4000 SSI1 */
|
|
/* 29 SSI1 SSI-1 Interrupt Request */
|
|
SSI1: ssi@83fcc000 {
|
|
compatible = "fsl,imx51-ssi";
|
|
reg = <0x83fcc000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <29>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 83FD0000 0x4000 AUDMUX */
|
|
audmux@83fd4000 {
|
|
compatible = "fsl,imx51-audmux";
|
|
reg = <0x83fd4000 0x4000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 83FD8000 0x4000 EMI1 */
|
|
/* 8 EMI (NFC) */
|
|
/* 15 EMI */
|
|
/* 97 EMI Boot sequence completed interrupt */
|
|
/*
|
|
* 101 EMI Indicates all pages have been transferred
|
|
* to NFC during an auto program operation.
|
|
*/
|
|
|
|
/* 83FE0000 0x4000 PATA (PORT PIO) */
|
|
/* 70 PATA Parallel ATA host controller interrupt */
|
|
ide@83fe0000 {
|
|
compatible = "fsl,imx51-ata";
|
|
reg = <0x83fe0000 0x4000>;
|
|
interrupt-parent = <&tzic>;
|
|
interrupts = <70>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 83FE4000 0x4000 SIM */
|
|
/* 67 SIM intr composed of oef, xte, sdi1, and sdi0 */
|
|
/* 68 SIM intr composed of tc, etc, tfe, and rdrf */
|
|
|
|
/* 83FE8000 0x4000 SSI3 */
|
|
/* 96 SSI3 SSI-3 Interrupt Request */
|
|
SSI3: ssi@83fe8000 {
|
|
compatible = "fsl,imx51-ssi";
|
|
reg = <0x83fe8000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <96>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 83FEC000 0x4000 FEC */
|
|
ethernet@83fec000 {
|
|
compatible = "fsl,imx51-fec";
|
|
reg = <0x83fec000 0x4000>;
|
|
interrupt-parent = <&tzic>; interrupts = <87>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* 83FF0000 0x4000 TVE */
|
|
/* 92 TVE */
|
|
/* 83FF4000 0x4000 VPU */
|
|
/* 9 VPU */
|
|
/* 100 VPU Idle interrupt from VPU */
|
|
|
|
/* 83FF8000 0x4000 SAHARA Lite */
|
|
/* 19 SAHARA SAHARA host 0 (TrustZone) Intr Lite */
|
|
/* 20 SAHARA SAHARA host 1 (non-TrustZone) Intr Lite */
|
|
};
|
|
};
|
|
|
|
localbus@5e000000 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
ranges;
|
|
|
|
vga: ipu3@5e000000 {
|
|
compatible = "fsl,ipu3";
|
|
reg = <
|
|
0x5e000000 0x08000 /* CM */
|
|
0x5e008000 0x08000 /* IDMAC */
|
|
0x5e018000 0x08000 /* DP */
|
|
0x5e020000 0x08000 /* IC */
|
|
0x5e028000 0x08000 /* IRT */
|
|
0x5e030000 0x08000 /* CSI0 */
|
|
0x5e038000 0x08000 /* CSI1 */
|
|
0x5e040000 0x08000 /* DI0 */
|
|
0x5e048000 0x08000 /* DI1 */
|
|
0x5e050000 0x08000 /* SMFC */
|
|
0x5e058000 0x08000 /* DC */
|
|
0x5e060000 0x08000 /* DMFC */
|
|
0x5e068000 0x08000 /* VDI */
|
|
0x5f000000 0x20000 /* CPMEM */
|
|
0x5f020000 0x20000 /* LUT */
|
|
0x5f040000 0x20000 /* SRM */
|
|
0x5f060000 0x20000 /* TPM */
|
|
0x5f080000 0x20000 /* DCTMPL */
|
|
>;
|
|
interrupt-parent = <&tzic>;
|
|
interrupts = <
|
|
10 /* IPUEX Error */
|
|
11 /* IPUEX Sync */
|
|
>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
|
|
/*
|
|
|
|
TODO: Not mapped interrupts
|
|
|
|
5 DAP
|
|
84 GPU2D (OpenVG) general interrupt
|
|
85 GPU2D (OpenVG) busy signal (for S/W power gating feasibility)
|
|
12 GPU3D
|
|
102 GPU3D Idle interrupt from GPU3D (for S/W power gating)
|
|
90 SJC
|
|
*/
|