a9ca1c79c6
Add support for two new devices: X552 SFP+ 10 GbE, and the single port version of X550T. Submitted by: erj Reviewed by: gnn Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D4186
744 lines
22 KiB
C
744 lines
22 KiB
C
/******************************************************************************
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Copyright (c) 2001-2015, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "ixgbe_type.h"
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#include "ixgbe_dcb.h"
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#include "ixgbe_dcb_82598.h"
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#include "ixgbe_dcb_82599.h"
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/**
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* ixgbe_dcb_calculate_tc_credits - This calculates the ieee traffic class
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* credits from the configured bandwidth percentages. Credits
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* are the smallest unit programmable into the underlying
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* hardware. The IEEE 802.1Qaz specification do not use bandwidth
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* groups so this is much simplified from the CEE case.
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*/
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s32 ixgbe_dcb_calculate_tc_credits(u8 *bw, u16 *refill, u16 *max,
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int max_frame_size)
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{
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int min_percent = 100;
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int min_credit, multiplier;
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int i;
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min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
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IXGBE_DCB_CREDIT_QUANTUM;
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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if (bw[i] < min_percent && bw[i])
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min_percent = bw[i];
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}
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multiplier = (min_credit / min_percent) + 1;
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/* Find out the hw credits for each TC */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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int val = min(bw[i] * multiplier, IXGBE_DCB_MAX_CREDIT_REFILL);
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if (val < min_credit)
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val = min_credit;
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refill[i] = (u16)val;
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max[i] = bw[i] ? (bw[i]*IXGBE_DCB_MAX_CREDIT)/100 : min_credit;
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}
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return 0;
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}
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/**
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* ixgbe_dcb_calculate_tc_credits_cee - Calculates traffic class credits
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* @ixgbe_dcb_config: Struct containing DCB settings.
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* @direction: Configuring either Tx or Rx.
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*
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* This function calculates the credits allocated to each traffic class.
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* It should be called only after the rules are checked by
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* ixgbe_dcb_check_config_cee().
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*/
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s32 ixgbe_dcb_calculate_tc_credits_cee(struct ixgbe_hw *hw,
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struct ixgbe_dcb_config *dcb_config,
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u32 max_frame_size, u8 direction)
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{
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struct ixgbe_dcb_tc_path *p;
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u32 min_multiplier = 0;
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u16 min_percent = 100;
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s32 ret_val = IXGBE_SUCCESS;
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/* Initialization values default for Tx settings */
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u32 min_credit = 0;
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u32 credit_refill = 0;
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u32 credit_max = 0;
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u16 link_percentage = 0;
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u8 bw_percent = 0;
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u8 i;
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if (dcb_config == NULL) {
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ret_val = IXGBE_ERR_CONFIG;
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goto out;
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}
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min_credit = ((max_frame_size / 2) + IXGBE_DCB_CREDIT_QUANTUM - 1) /
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IXGBE_DCB_CREDIT_QUANTUM;
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/* Find smallest link percentage */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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p = &dcb_config->tc_config[i].path[direction];
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bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
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link_percentage = p->bwg_percent;
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link_percentage = (link_percentage * bw_percent) / 100;
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if (link_percentage && link_percentage < min_percent)
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min_percent = link_percentage;
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}
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/*
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* The ratio between traffic classes will control the bandwidth
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* percentages seen on the wire. To calculate this ratio we use
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* a multiplier. It is required that the refill credits must be
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* larger than the max frame size so here we find the smallest
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* multiplier that will allow all bandwidth percentages to be
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* greater than the max frame size.
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*/
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min_multiplier = (min_credit / min_percent) + 1;
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/* Find out the link percentage for each TC first */
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for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
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p = &dcb_config->tc_config[i].path[direction];
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bw_percent = dcb_config->bw_percentage[direction][p->bwg_id];
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link_percentage = p->bwg_percent;
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/* Must be careful of integer division for very small nums */
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link_percentage = (link_percentage * bw_percent) / 100;
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if (p->bwg_percent > 0 && link_percentage == 0)
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link_percentage = 1;
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/* Save link_percentage for reference */
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p->link_percent = (u8)link_percentage;
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/* Calculate credit refill ratio using multiplier */
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credit_refill = min(link_percentage * min_multiplier,
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(u32)IXGBE_DCB_MAX_CREDIT_REFILL);
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/* Refill at least minimum credit */
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if (credit_refill < min_credit)
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credit_refill = min_credit;
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p->data_credits_refill = (u16)credit_refill;
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/* Calculate maximum credit for the TC */
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credit_max = (link_percentage * IXGBE_DCB_MAX_CREDIT) / 100;
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/*
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* Adjustment based on rule checking, if the percentage
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* of a TC is too small, the maximum credit may not be
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* enough to send out a jumbo frame in data plane arbitration.
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*/
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if (credit_max < min_credit)
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credit_max = min_credit;
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if (direction == IXGBE_DCB_TX_CONFIG) {
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/*
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* Adjustment based on rule checking, if the
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* percentage of a TC is too small, the maximum
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* credit may not be enough to send out a TSO
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* packet in descriptor plane arbitration.
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*/
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if (credit_max && (credit_max <
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IXGBE_DCB_MIN_TSO_CREDIT)
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&& (hw->mac.type == ixgbe_mac_82598EB))
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credit_max = IXGBE_DCB_MIN_TSO_CREDIT;
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dcb_config->tc_config[i].desc_credits_max =
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(u16)credit_max;
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}
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p->data_credits_max = (u16)credit_max;
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}
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out:
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return ret_val;
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}
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/**
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* ixgbe_dcb_unpack_pfc_cee - Unpack dcb_config PFC info
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* @cfg: dcb configuration to unpack into hardware consumable fields
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* @map: user priority to traffic class map
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* @pfc_up: u8 to store user priority PFC bitmask
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*
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* This unpacks the dcb configuration PFC info which is stored per
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* traffic class into a 8bit user priority bitmask that can be
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* consumed by hardware routines. The priority to tc map must be
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* updated before calling this routine to use current up-to maps.
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*/
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void ixgbe_dcb_unpack_pfc_cee(struct ixgbe_dcb_config *cfg, u8 *map, u8 *pfc_up)
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{
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struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
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int up;
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/*
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* If the TC for this user priority has PFC enabled then set the
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* matching bit in 'pfc_up' to reflect that PFC is enabled.
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*/
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for (*pfc_up = 0, up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++) {
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if (tc_config[map[up]].pfc != ixgbe_dcb_pfc_disabled)
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*pfc_up |= 1 << up;
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}
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}
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void ixgbe_dcb_unpack_refill_cee(struct ixgbe_dcb_config *cfg, int direction,
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u16 *refill)
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{
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struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
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int tc;
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for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
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refill[tc] = tc_config[tc].path[direction].data_credits_refill;
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}
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void ixgbe_dcb_unpack_max_cee(struct ixgbe_dcb_config *cfg, u16 *max)
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{
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struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
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int tc;
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for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
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max[tc] = tc_config[tc].desc_credits_max;
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}
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void ixgbe_dcb_unpack_bwgid_cee(struct ixgbe_dcb_config *cfg, int direction,
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u8 *bwgid)
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{
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struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
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int tc;
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for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
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bwgid[tc] = tc_config[tc].path[direction].bwg_id;
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}
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void ixgbe_dcb_unpack_tsa_cee(struct ixgbe_dcb_config *cfg, int direction,
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u8 *tsa)
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{
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struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
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int tc;
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for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++)
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tsa[tc] = tc_config[tc].path[direction].tsa;
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}
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u8 ixgbe_dcb_get_tc_from_up(struct ixgbe_dcb_config *cfg, int direction, u8 up)
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{
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struct ixgbe_dcb_tc_config *tc_config = &cfg->tc_config[0];
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u8 prio_mask = 1 << up;
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u8 tc = cfg->num_tcs.pg_tcs;
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/* If tc is 0 then DCB is likely not enabled or supported */
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if (!tc)
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goto out;
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/*
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* Test from maximum TC to 1 and report the first match we find. If
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* we find no match we can assume that the TC is 0 since the TC must
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* be set for all user priorities
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*/
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for (tc--; tc; tc--) {
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if (prio_mask & tc_config[tc].path[direction].up_to_tc_bitmap)
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break;
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}
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out:
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return tc;
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}
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void ixgbe_dcb_unpack_map_cee(struct ixgbe_dcb_config *cfg, int direction,
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u8 *map)
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{
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u8 up;
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for (up = 0; up < IXGBE_DCB_MAX_USER_PRIORITY; up++)
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map[up] = ixgbe_dcb_get_tc_from_up(cfg, direction, up);
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}
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/**
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* ixgbe_dcb_config - Struct containing DCB settings.
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* @dcb_config: Pointer to DCB config structure
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*
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* This function checks DCB rules for DCB settings.
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* The following rules are checked:
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* 1. The sum of bandwidth percentages of all Bandwidth Groups must total 100%.
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* 2. The sum of bandwidth percentages of all Traffic Classes within a Bandwidth
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* Group must total 100.
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* 3. A Traffic Class should not be set to both Link Strict Priority
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* and Group Strict Priority.
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* 4. Link strict Bandwidth Groups can only have link strict traffic classes
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* with zero bandwidth.
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*/
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s32 ixgbe_dcb_check_config_cee(struct ixgbe_dcb_config *dcb_config)
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{
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struct ixgbe_dcb_tc_path *p;
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s32 ret_val = IXGBE_SUCCESS;
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u8 i, j, bw = 0, bw_id;
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u8 bw_sum[2][IXGBE_DCB_MAX_BW_GROUP];
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bool link_strict[2][IXGBE_DCB_MAX_BW_GROUP];
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memset(bw_sum, 0, sizeof(bw_sum));
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memset(link_strict, 0, sizeof(link_strict));
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/* First Tx, then Rx */
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for (i = 0; i < 2; i++) {
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/* Check each traffic class for rule violation */
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for (j = 0; j < IXGBE_DCB_MAX_TRAFFIC_CLASS; j++) {
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p = &dcb_config->tc_config[j].path[i];
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bw = p->bwg_percent;
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bw_id = p->bwg_id;
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if (bw_id >= IXGBE_DCB_MAX_BW_GROUP) {
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ret_val = IXGBE_ERR_CONFIG;
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goto err_config;
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}
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if (p->tsa == ixgbe_dcb_tsa_strict) {
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link_strict[i][bw_id] = TRUE;
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/* Link strict should have zero bandwidth */
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if (bw) {
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ret_val = IXGBE_ERR_CONFIG;
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goto err_config;
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}
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} else if (!bw) {
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/*
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* Traffic classes without link strict
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* should have non-zero bandwidth.
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*/
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ret_val = IXGBE_ERR_CONFIG;
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goto err_config;
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}
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bw_sum[i][bw_id] += bw;
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}
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bw = 0;
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/* Check each bandwidth group for rule violation */
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for (j = 0; j < IXGBE_DCB_MAX_BW_GROUP; j++) {
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bw += dcb_config->bw_percentage[i][j];
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/*
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* Sum of bandwidth percentages of all traffic classes
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* within a Bandwidth Group must total 100 except for
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* link strict group (zero bandwidth).
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*/
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if (link_strict[i][j]) {
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if (bw_sum[i][j]) {
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/*
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* Link strict group should have zero
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* bandwidth.
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*/
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ret_val = IXGBE_ERR_CONFIG;
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goto err_config;
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}
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} else if (bw_sum[i][j] != IXGBE_DCB_BW_PERCENT &&
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bw_sum[i][j] != 0) {
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ret_val = IXGBE_ERR_CONFIG;
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goto err_config;
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}
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}
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if (bw != IXGBE_DCB_BW_PERCENT) {
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ret_val = IXGBE_ERR_CONFIG;
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goto err_config;
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}
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}
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err_config:
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DEBUGOUT2("DCB error code %d while checking %s settings.\n",
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ret_val, (i == IXGBE_DCB_TX_CONFIG) ? "Tx" : "Rx");
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return ret_val;
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}
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/**
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* ixgbe_dcb_get_tc_stats - Returns status of each traffic class
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* @hw: pointer to hardware structure
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* @stats: pointer to statistics structure
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* @tc_count: Number of elements in bwg_array.
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*
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* This function returns the status data for each of the Traffic Classes in use.
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*/
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s32 ixgbe_dcb_get_tc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
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u8 tc_count)
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{
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s32 ret = IXGBE_NOT_IMPLEMENTED;
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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ret = ixgbe_dcb_get_tc_stats_82598(hw, stats, tc_count);
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
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ret = ixgbe_dcb_get_tc_stats_82599(hw, stats, tc_count);
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break;
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#endif
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default:
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break;
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}
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return ret;
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}
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/**
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* ixgbe_dcb_get_pfc_stats - Returns CBFC status of each traffic class
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* @hw: pointer to hardware structure
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* @stats: pointer to statistics structure
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* @tc_count: Number of elements in bwg_array.
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*
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* This function returns the CBFC status data for each of the Traffic Classes.
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*/
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s32 ixgbe_dcb_get_pfc_stats(struct ixgbe_hw *hw, struct ixgbe_hw_stats *stats,
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u8 tc_count)
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{
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s32 ret = IXGBE_NOT_IMPLEMENTED;
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switch (hw->mac.type) {
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case ixgbe_mac_82598EB:
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ret = ixgbe_dcb_get_pfc_stats_82598(hw, stats, tc_count);
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break;
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case ixgbe_mac_82599EB:
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case ixgbe_mac_X540:
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case ixgbe_mac_X550:
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case ixgbe_mac_X550EM_x:
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#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
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ret = ixgbe_dcb_get_pfc_stats_82599(hw, stats, tc_count);
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break;
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#endif
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default:
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break;
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}
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return ret;
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}
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/**
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* ixgbe_dcb_config_rx_arbiter_cee - Config Rx arbiter
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* @hw: pointer to hardware structure
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* @dcb_config: pointer to ixgbe_dcb_config structure
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*
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* Configure Rx Data Arbiter and credits for each traffic class.
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*/
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s32 ixgbe_dcb_config_rx_arbiter_cee(struct ixgbe_hw *hw,
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struct ixgbe_dcb_config *dcb_config)
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{
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s32 ret = IXGBE_NOT_IMPLEMENTED;
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u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
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u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
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u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
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u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
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u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS] = { 0 };
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ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
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|
ixgbe_dcb_unpack_max_cee(dcb_config, max);
|
|
ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
|
|
ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
|
|
ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ret = ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ret = ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwgid,
|
|
tsa, map);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_dcb_config_tx_desc_arbiter_cee - Config Tx Desc arbiter
|
|
* @hw: pointer to hardware structure
|
|
* @dcb_config: pointer to ixgbe_dcb_config structure
|
|
*
|
|
* Configure Tx Descriptor Arbiter and credits for each traffic class.
|
|
*/
|
|
s32 ixgbe_dcb_config_tx_desc_arbiter_cee(struct ixgbe_hw *hw,
|
|
struct ixgbe_dcb_config *dcb_config)
|
|
{
|
|
s32 ret = IXGBE_NOT_IMPLEMENTED;
|
|
u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
|
|
ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
|
|
ixgbe_dcb_unpack_max_cee(dcb_config, max);
|
|
ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
|
|
ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ret = ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max,
|
|
bwgid, tsa);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ret = ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max,
|
|
bwgid, tsa);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_dcb_config_tx_data_arbiter_cee - Config Tx data arbiter
|
|
* @hw: pointer to hardware structure
|
|
* @dcb_config: pointer to ixgbe_dcb_config structure
|
|
*
|
|
* Configure Tx Data Arbiter and credits for each traffic class.
|
|
*/
|
|
s32 ixgbe_dcb_config_tx_data_arbiter_cee(struct ixgbe_hw *hw,
|
|
struct ixgbe_dcb_config *dcb_config)
|
|
{
|
|
s32 ret = IXGBE_NOT_IMPLEMENTED;
|
|
u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
|
|
u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
|
|
ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
|
|
ixgbe_dcb_unpack_max_cee(dcb_config, max);
|
|
ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
|
|
ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
|
|
ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ret = ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max,
|
|
bwgid, tsa);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ret = ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max,
|
|
bwgid, tsa,
|
|
map);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_dcb_config_pfc_cee - Config priority flow control
|
|
* @hw: pointer to hardware structure
|
|
* @dcb_config: pointer to ixgbe_dcb_config structure
|
|
*
|
|
* Configure Priority Flow Control for each traffic class.
|
|
*/
|
|
s32 ixgbe_dcb_config_pfc_cee(struct ixgbe_hw *hw,
|
|
struct ixgbe_dcb_config *dcb_config)
|
|
{
|
|
s32 ret = IXGBE_NOT_IMPLEMENTED;
|
|
u8 pfc_en;
|
|
u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
|
|
|
|
ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
|
|
ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_dcb_config_tc_stats - Config traffic class statistics
|
|
* @hw: pointer to hardware structure
|
|
*
|
|
* Configure queue statistics registers, all queues belonging to same traffic
|
|
* class uses a single set of queue statistics counters.
|
|
*/
|
|
s32 ixgbe_dcb_config_tc_stats(struct ixgbe_hw *hw)
|
|
{
|
|
s32 ret = IXGBE_NOT_IMPLEMENTED;
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ret = ixgbe_dcb_config_tc_stats_82598(hw);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ret = ixgbe_dcb_config_tc_stats_82599(hw, NULL);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* ixgbe_dcb_hw_config_cee - Config and enable DCB
|
|
* @hw: pointer to hardware structure
|
|
* @dcb_config: pointer to ixgbe_dcb_config structure
|
|
*
|
|
* Configure dcb settings and enable dcb mode.
|
|
*/
|
|
s32 ixgbe_dcb_hw_config_cee(struct ixgbe_hw *hw,
|
|
struct ixgbe_dcb_config *dcb_config)
|
|
{
|
|
s32 ret = IXGBE_NOT_IMPLEMENTED;
|
|
u8 pfc_en;
|
|
u8 tsa[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u8 bwgid[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u8 map[IXGBE_DCB_MAX_USER_PRIORITY] = { 0 };
|
|
u16 refill[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
u16 max[IXGBE_DCB_MAX_TRAFFIC_CLASS];
|
|
|
|
/* Unpack CEE standard containers */
|
|
ixgbe_dcb_unpack_refill_cee(dcb_config, IXGBE_DCB_TX_CONFIG, refill);
|
|
ixgbe_dcb_unpack_max_cee(dcb_config, max);
|
|
ixgbe_dcb_unpack_bwgid_cee(dcb_config, IXGBE_DCB_TX_CONFIG, bwgid);
|
|
ixgbe_dcb_unpack_tsa_cee(dcb_config, IXGBE_DCB_TX_CONFIG, tsa);
|
|
ixgbe_dcb_unpack_map_cee(dcb_config, IXGBE_DCB_TX_CONFIG, map);
|
|
|
|
hw->mac.ops.setup_rxpba(hw, dcb_config->num_tcs.pg_tcs,
|
|
0, dcb_config->rx_pba_cfg);
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ret = ixgbe_dcb_hw_config_82598(hw, dcb_config->link_speed,
|
|
refill, max, bwgid, tsa);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ixgbe_dcb_config_82599(hw, dcb_config);
|
|
ret = ixgbe_dcb_hw_config_82599(hw, dcb_config->link_speed,
|
|
refill, max, bwgid,
|
|
tsa, map);
|
|
|
|
ixgbe_dcb_config_tc_stats_82599(hw, dcb_config);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
|
|
if (!ret && dcb_config->pfc_mode_enable) {
|
|
ixgbe_dcb_unpack_pfc_cee(dcb_config, map, &pfc_en);
|
|
ret = ixgbe_dcb_config_pfc(hw, pfc_en, map);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* Helper routines to abstract HW specifics from DCB netlink ops */
|
|
s32 ixgbe_dcb_config_pfc(struct ixgbe_hw *hw, u8 pfc_en, u8 *map)
|
|
{
|
|
int ret = IXGBE_ERR_PARAM;
|
|
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ret = ixgbe_dcb_config_pfc_82598(hw, pfc_en);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ret = ixgbe_dcb_config_pfc_82599(hw, pfc_en, map);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
s32 ixgbe_dcb_hw_config(struct ixgbe_hw *hw, u16 *refill, u16 *max,
|
|
u8 *bwg_id, u8 *tsa, u8 *map)
|
|
{
|
|
switch (hw->mac.type) {
|
|
case ixgbe_mac_82598EB:
|
|
ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
|
|
ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
|
|
tsa);
|
|
ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
|
|
tsa);
|
|
break;
|
|
case ixgbe_mac_82599EB:
|
|
case ixgbe_mac_X540:
|
|
case ixgbe_mac_X550:
|
|
case ixgbe_mac_X550EM_x:
|
|
#if !defined(NO_82599_SUPPORT) || !defined(NO_X540_SUPPORT)
|
|
ixgbe_dcb_config_rx_arbiter_82599(hw, refill, max, bwg_id,
|
|
tsa, map);
|
|
ixgbe_dcb_config_tx_desc_arbiter_82599(hw, refill, max, bwg_id,
|
|
tsa);
|
|
ixgbe_dcb_config_tx_data_arbiter_82599(hw, refill, max, bwg_id,
|
|
tsa, map);
|
|
break;
|
|
#endif
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|