c3dd1fa899
Host ATM Research Platform (HARP), Network Computing Services, Inc. This software was developed with the support of the Defense Advanced Research Projects Agency (DARPA).
192 lines
5.7 KiB
C
192 lines
5.7 KiB
C
/*
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*
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* ===================================
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* HARP | Host ATM Research Platform
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* ===================================
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*
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*
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* This Host ATM Research Platform ("HARP") file (the "Software") is
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* made available by Network Computing Services, Inc. ("NetworkCS")
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* "AS IS". NetworkCS does not provide maintenance, improvements or
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* support of any kind.
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*
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* NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
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* INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
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* SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
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* In no event shall NetworkCS be responsible for any damages, including
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* but not limited to consequential damages, arising from or relating to
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* any use of the Software or related support.
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*
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* Copyright 1994-1998 Network Computing Services, Inc.
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*
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* Copies of this Software may be made, however, the above copyright
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* notice must be reproduced on all copies.
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*
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* @(#) $Id: fore_slave.h,v 1.5 1997/08/22 19:45:50 jpt Exp $
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*
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*/
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/*
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* FORE Systems 200-Series Adapter Support
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* ---------------------------------------
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*
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* Slave Interface definitions
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*
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*/
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#ifndef _FORE_SLAVE_H
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#define _FORE_SLAVE_H
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/*
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* This file contains the (mostly hardware) definitions for each of the
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* supported 200-series slave interfaces.
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*/
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/*
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* Structure defining the supported FORE 200-series interfaces
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*/
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struct fore_device {
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char *fd_name; /* Device name (from PROM) */
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Atm_device fd_devtyp; /* Device type */
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};
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typedef struct fore_device Fore_device;
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/*
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* Common definitions
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* ------------------
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*/
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#define MON960_BASE 0x400 /* Address offset of Mon960 */
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#define AALI_BASE 0x4d40 /* Address offset of Aali */
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typedef volatile unsigned int Fore_reg; /* Slave control register */
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typedef volatile unsigned char Fore_mem; /* Slave memory */
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/*
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* SBA-200E SBus Slave Interface
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* -----------------------------
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*/
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#define SBA200E_PROM_NAME "FORE,sba-200e"
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/*
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* SBA-200E Host Control Register (HCR)
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*/
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#define SBA200E_READ_BITS 0x1ff /* Valid read data bits */
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#define SBA200E_WRITE_BITS 0x01f /* Valid write data bits */
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#define SBA200E_STICKY_BITS 0x013 /* Sticky data bits */
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/* Read access */
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#define SBA200E_SBUS_INTR_RD 0x100 /* State of SBus interrupt */
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#define SBA200E_TEST_MODE 0x080 /* Device is in test-mode */
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#define SBA200E_IFIFO_FULL 0x040 /* Input FIFO almost full (when 0) */
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#define SBA200E_ESP_HOLD_RD 0x020 /* State of ESP bus hold */
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#define SBA200E_SBUS_ENA_RD 0x010 /* State of SBus interrupt enable */
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#define SBA200E_OFIFO_FULL 0x008 /* Output FIFO almost full */
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#define SBA200E_SELFTEST_FAIL 0x004 /* i960 self-test failed (when 0) */
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#define SBA200E_HOLD_LOCK_RD 0x002 /* State of i960 hold lock signal */
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#define SBA200E_RESET_RD 0x001 /* State of board reset signal */
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/* Write access - bit set (clear) */
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#define SBA200E_SBUS_ENA 0x010 /* Enable (disable) SBus interrupts */
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#define SBA200E_CLR_SBUS_INTR 0x008 /* Clear SBus interrupt */
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#define SBA200E_I960_INTR 0x004 /* Issue interrupt to i960 */
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#define SBA200E_HOLD_LOCK 0x002 /* Set (clear) i960 hold lock signal */
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#define SBA200E_RESET 0x001 /* Set (clear) board reset signal */
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#define SBA200E_HCR_INIT(hcr,bits) \
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((hcr) = (SBA200E_WRITE_BITS & (bits)))
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#define SBA200E_HCR_SET(hcr,bits) \
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((hcr) = (((hcr) & SBA200E_STICKY_BITS) | (bits)))
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#define SBA200E_HCR_CLR(hcr,bits) \
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((hcr) = ((hcr) & (SBA200E_STICKY_BITS ^ (bits))))
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/*
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* SBA-200 SBus Slave Interface
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* ----------------------------
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*/
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#define SBA200_PROM_NAME "FORE,sba-200"
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/*
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* SBA-200 Board Control Register (BCR)
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*/
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/* Write access - bit set */
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#define SBA200_CLR_SBUS_INTR 0x04 /* Clear SBus interrupt */
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#define SBA200_RESET 0x01 /* Assert board reset signal */
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/* Write access - bit clear */
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#define SBA200_RESET_CLR 0x00 /* Clear board reset signal */
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/*
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* PCA-200E PCI Bus Slave Interface
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* --------------------------------
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*/
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/*
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* PCI Identifiers
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*/
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#define FORE_VENDOR_ID 0x1127
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#define FORE_PCA200E_ID 0x0300
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/*
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* PCA-200E PCI Configuration Space
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*/
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#define PCA200E_PCI_MEMBASE 0x10 /* Memory base address */
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#define PCA200E_PCI_MCTL 0x40 /* Master control */
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/*
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* PCA-200E Address Space
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*/
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#define PCA200E_RAM_SIZE 0x100000
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#define PCA200E_HCR_OFFSET 0x100000
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#define PCA200E_IMASK_OFFSET 0x100004
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#define PCA200E_PSR_OFFSET 0x100008
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#define PCA200E_MMAP_SIZE 0x10000c
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/*
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* PCA-200E Master Control
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*/
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#define PCA200E_MCTL_SWAP 0x4000 /* Convert Slave endianess */
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/*
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* PCA-200E Host Control Register (HCR)
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*/
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#define PCA200E_READ_BITS 0x0ff /* Valid read data bits */
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#define PCA200E_WRITE_BITS 0x01f /* Valid write data bits */
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#define PCA200E_STICKY_BITS 0x000 /* Sticky data bits */
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/* Read access */
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#define PCA200E_TEST_MODE 0x080 /* Device is in test-mode */
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#define PCA200E_IFIFO_FULL 0x040 /* Input FIFO almost full */
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#define PCA200E_ESP_HOLD_RD 0x020 /* State of ESP hold bus */
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#define PCA200E_OFIFO_FULL 0x010 /* Output FIFO almost full */
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#define PCA200E_HOLD_ACK 0x008 /* State of Hold Ack */
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#define PCA200E_SELFTEST_FAIL 0x004 /* i960 self-test failed */
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#define PCA200E_HOLD_LOCK_RD 0x002 /* State of i960 hold lock signal */
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#define PCA200E_RESET_BD 0x001 /* State of board reset signal */
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/* Write access */
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#define PCA200E_CLR_HBUS_INT 0x010 /* Clear host bus interrupt */
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#define PCA200E_I960_INTRA 0x008 /* Set slave interrupt A */
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#define PCA200E_I960_INTRB 0x004 /* Set slave interrupt B */
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#define PCA200E_HOLD_LOCK 0x002 /* Set (clear) i960 hold lock signal */
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#define PCA200E_RESET 0x001 /* Set (clear) board reset signal */
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#define PCA200E_HCR_INIT(hcr,bits) \
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((hcr) = (PCA200E_WRITE_BITS & (bits)))
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#define PCA200E_HCR_SET(hcr,bits) \
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((hcr) = (bits))
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#define PCA200E_HCR_CLR(hcr,bits) \
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((hcr) = 0)
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#endif /* _FORE_SLAVE_H */
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