c3dd1fa899
Host ATM Research Platform (HARP), Network Computing Services, Inc. This software was developed with the support of the Defense Advanced Research Projects Agency (DARPA).
270 lines
8.3 KiB
C
270 lines
8.3 KiB
C
/*
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*
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* ===================================
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* HARP | Host ATM Research Platform
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* ===================================
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*
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*
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* This Host ATM Research Platform ("HARP") file (the "Software") is
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* made available by Network Computing Services, Inc. ("NetworkCS")
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* "AS IS". NetworkCS does not provide maintenance, improvements or
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* support of any kind.
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*
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* NETWORKCS MAKES NO WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED,
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* INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE, AS TO ANY ELEMENT OF THE
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* SOFTWARE OR ANY SUPPORT PROVIDED IN CONNECTION WITH THIS SOFTWARE.
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* In no event shall NetworkCS be responsible for any damages, including
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* but not limited to consequential damages, arising from or relating to
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* any use of the Software or related support.
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*
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* Copyright 1994-1998 Network Computing Services, Inc.
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*
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* Copies of this Software may be made, however, the above copyright
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* notice must be reproduced on all copies.
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*
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* @(#) $Id: fore_var.h,v 1.8 1998/02/19 20:10:53 mks Exp $
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*
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*/
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/*
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* FORE Systems 200-Series Adapter Support
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* ---------------------------------------
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*
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* Host protocol control blocks
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*
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*/
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#ifndef _FORE_VAR_H
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#define _FORE_VAR_H
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/*
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* Device VCC Entry
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*
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* Contains the common and Fore-specific information for each VCC
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* which is opened through a Fore device.
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*/
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struct fore_vcc {
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struct cmn_vcc fv_cmn; /* Common VCC stuff */
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Fore_aal fv_aal; /* CP version of AAL */
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};
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typedef struct fore_vcc Fore_vcc;
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#define fv_next fv_cmn.cv_next
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#define fv_toku fv_cmn.cv_toku
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#define fv_upper fv_cmn.cv_upper
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#define fv_connvc fv_cmn.cv_connvc
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#define fv_state fv_cmn.cv_state
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#define fv_flags fv_cmn.cv_flags
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/*
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* VCC Flags
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*/
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#define FVF_ACTCMD 0x01 /* Activate command issued */
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/*
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* Host Transmit Queue Element
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*
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* Defines the host's view of the CP PDU Transmit Queue
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*/
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struct h_xmit_queue {
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struct h_xmit_queue *hxq_next; /* Next element in queue */
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Xmit_queue *hxq_cpelem; /* CP queue element */
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Q_status *hxq_status; /* Element status word */
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Xmit_descr *hxq_descr; /* Element's transmit descriptor */
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Xmit_descr *hxq_descr_dma; /* Element's transmit descriptor */
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Fore_vcc *hxq_vcc; /* Data's VCC */
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KBuffer *hxq_buf; /* Data's buffer chain head */
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H_dma hxq_dma[XMIT_MAX_SEGS]; /* DMA addresses for segments */
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};
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typedef struct h_xmit_queue H_xmit_queue;
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/*
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* Host Receive Queue Element
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*
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* Defines the host's view of the CP PDU Receive Queue
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*/
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struct h_recv_queue {
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struct h_recv_queue *hrq_next; /* Next element in queue */
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Recv_queue *hrq_cpelem; /* CP queue element */
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Q_status *hrq_status; /* Element status word */
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Recv_descr *hrq_descr; /* Element's receive descriptor */
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Recv_descr *hrq_descr_dma; /* Element's receive descriptor */
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};
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typedef struct h_recv_queue H_recv_queue;
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/*
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* Host Buffer Supply Queue Element
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*
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* Defines the host's view of the CP Buffer Supply Queue
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*/
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struct h_buf_queue {
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struct h_buf_queue *hbq_next; /* Next element in queue */
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Buf_queue *hbq_cpelem; /* CP queue element */
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Q_status *hbq_status; /* Element status word */
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Buf_descr *hbq_descr; /* Element's buffer descriptor array */
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Buf_descr *hbq_descr_dma; /* Element's buffer descriptor array */
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};
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typedef struct h_buf_queue H_buf_queue;
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/*
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* Host Command Queue Element
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*
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* Defines the host's view of the CP Command Queue
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*/
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struct h_cmd_queue {
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struct h_cmd_queue *hcq_next; /* Next element in queue */
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Cmd_queue *hcq_cpelem; /* CP queue element */
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Q_status *hcq_status; /* Element status word */
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Cmd_code hcq_code; /* Command code */
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void *hcq_arg; /* Command-specific argument */
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};
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typedef struct h_cmd_queue H_cmd_queue;
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/*
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* Host Buffer Handle
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*
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* For each buffer supplied to the CP, there will be one of these structures
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* embedded into the non-data portion of the buffer. This will allow us to
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* track which buffers are currently "controlled" by the CP. The address of
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* this structure will supplied to/returned from the CP as the buffer handle.
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*/
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struct buf_handle {
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Qelem_t bh_qelem; /* Queuing element */
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u_int bh_type; /* Buffer type (see below) */
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H_dma bh_dma; /* Buffer DMA address */
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};
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typedef struct buf_handle Buf_handle;
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#define SIZEOF_Buf_handle 16
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/*
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* Buffer Types
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*/
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#define BHT_S1_SMALL 1 /* Buffer strategy 1, small */
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#define BHT_S1_LARGE 2 /* Buffer strategy 1, large */
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#define BHT_S2_SMALL 3 /* Buffer strategy 2, small */
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#define BHT_S2_LARGE 4 /* Buffer strategy 2, large */
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/*
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* Device Unit Structure
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*
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* Contains all the information for a single device (adapter).
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*/
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struct fore_unit {
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Cmn_unit fu_cmn; /* Common unit stuff */
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#ifdef sun
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struct dev_info *fu_devinfo; /* Device node for this unit */
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#endif
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Fore_reg *fu_ctlreg; /* Device control register */
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#ifdef FORE_SBUS
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Fore_reg *fu_intlvl; /* Interrupt level register */
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#endif
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#ifdef FORE_PCI
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Fore_reg *fu_imask; /* Interrupt mask register */
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Fore_reg *fu_psr; /* PCI specific register */
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pcici_t fu_pcitag; /* PCI tag */
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#endif
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Fore_mem *fu_ram; /* Device RAM */
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u_int fu_ramsize; /* Size of device RAM */
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Mon960 *fu_mon; /* Monitor program interface */
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Aali *fu_aali; /* Microcode program interface */
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u_int fu_timer; /* Watchdog timer value */
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/* Transmit Queue */
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H_xmit_queue fu_xmit_q[XMIT_QUELEN]; /* Host queue */
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H_xmit_queue *fu_xmit_head; /* Queue head */
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H_xmit_queue *fu_xmit_tail; /* Queue tail */
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Q_status *fu_xmit_stat; /* Status array (host) */
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Q_status *fu_xmit_statd; /* Status array (DMA) */
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/* Receive Queue */
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H_recv_queue fu_recv_q[RECV_QUELEN]; /* Host queue */
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H_recv_queue *fu_recv_head; /* Queue head */
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Q_status *fu_recv_stat; /* Status array (host) */
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Q_status *fu_recv_statd; /* Status array (DMA) */
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Recv_descr *fu_recv_desc; /* Descriptor array (host) */
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Recv_descr *fu_recv_descd; /* Descriptor array (DMA) */
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/* Buffer Supply Queue - Strategy 1 Small */
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H_buf_queue fu_buf1s_q[BUF1_SM_QUELEN]; /* Host queue */
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H_buf_queue *fu_buf1s_head; /* Queue head */
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H_buf_queue *fu_buf1s_tail; /* Queue tail */
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Q_status *fu_buf1s_stat; /* Status array (host) */
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Q_status *fu_buf1s_statd;/* Status array (DMA) */
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Buf_descr *fu_buf1s_desc; /* Descriptor array (host) */
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Buf_descr *fu_buf1s_descd;/* Descriptor array (DMA) */
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Queue_t fu_buf1s_bq; /* Queue of supplied buffers */
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u_int fu_buf1s_cnt; /* Count of supplied buffers */
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/* Buffer Supply Queue - Strategy 1 Large */
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H_buf_queue fu_buf1l_q[BUF1_LG_QUELEN]; /* Host queue */
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H_buf_queue *fu_buf1l_head; /* Queue head */
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H_buf_queue *fu_buf1l_tail; /* Queue tail */
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Q_status *fu_buf1l_stat; /* Status array (host) */
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Q_status *fu_buf1l_statd;/* Status array (DMA) */
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Buf_descr *fu_buf1l_desc; /* Descriptor array (host) */
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Buf_descr *fu_buf1l_descd;/* Descriptor array (DMA) */
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Queue_t fu_buf1l_bq; /* Queue of supplied buffers */
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u_int fu_buf1l_cnt; /* Count of supplied buffers */
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/* Command Queue */
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H_cmd_queue fu_cmd_q[CMD_QUELEN]; /* Host queue */
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H_cmd_queue *fu_cmd_head; /* Queue head */
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H_cmd_queue *fu_cmd_tail; /* Queue tail */
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Q_status *fu_cmd_stat; /* Status array (host) */
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Q_status *fu_cmd_statd; /* Status array (DMA) */
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Fore_stats *fu_stats; /* Device statistics buffer */
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Fore_stats *fu_statsd; /* Device statistics buffer (DMA) */
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time_t fu_stats_time; /* Last stats request timestamp */
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int fu_stats_ret; /* Stats request return code */
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#ifdef FORE_PCI
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Fore_prom *fu_prom; /* Device PROM buffer */
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Fore_prom *fu_promd; /* Device PROM buffer (DMA) */
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#endif
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struct callout_handle fu_thandle; /* Timer handle */
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};
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typedef struct fore_unit Fore_unit;
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#define fu_pif fu_cmn.cu_pif
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#define fu_unit fu_cmn.cu_unit
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#define fu_flags fu_cmn.cu_flags
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#define fu_mtu fu_cmn.cu_mtu
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#define fu_open_vcc fu_cmn.cu_open_vcc
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#define fu_vcc fu_cmn.cu_vcc
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#define fu_intrpri fu_cmn.cu_intrpri
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#define fu_savepri fu_cmn.cu_savepri
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#define fu_vcc_pool fu_cmn.cu_vcc_pool
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#define fu_nif_pool fu_cmn.cu_nif_pool
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#define fu_ioctl fu_cmn.cu_ioctl
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#define fu_instvcc fu_cmn.cu_instvcc
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#define fu_openvcc fu_cmn.cu_openvcc
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#define fu_closevcc fu_cmn.cu_closevcc
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#define fu_output fu_cmn.cu_output
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#define fu_config fu_cmn.cu_config
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/*
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* Device flags (in addition to CUF_* flags)
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*/
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#define FUF_STATCMD 0x80 /* Statistics request in progress */
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/*
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* Macros to access CP memory
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*/
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#define CP_READ(x) ntohl((u_long)(x))
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#define CP_WRITE(x) htonl((u_long)(x))
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#endif /* _FORE_VAR_H */
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