jhb f5760f10df Bump CACHE_LINE_SIZE to 128 for x86. Intel's manuals explicitly recommend ...

using 128 byte alignment for locks.  (See IA-32 SDM Vol 3A 7.11.6.7)

2009-05-18 19:33:59 +00:00

..

acpica

Reduce code duplcations from r190620. While I am here, tweak a comment.

2009-04-02 01:46:57 +00:00

amd64

Add cpu_flush_dcache() for use after non-DMA based I/O so that a

2009-05-18 18:37:18 +00:00

compile

Clone Kip's Xen on stable/6 tree so that I can work on improving FreeBSD/amd64

2008-11-22 16:14:52 +00:00

conf

Trim the default set of device hints on i386 and amd64:

2009-05-14 21:53:35 +00:00

ia32

Save and restore segment registers on amd64 when entering and leaving

2009-04-01 13:09:26 +00:00

include

Bump CACHE_LINE_SIZE to 128 for x86. Intel's manuals explicitly recommend

2009-05-18 19:33:59 +00:00

isa

Rename statclock_disable variable to atrtcclock_disable that it actually is,

2009-05-03 17:47:21 +00:00

linux32

Somewhere between 2.6.23 and 2.6.27, Linux added SOCK_CLOEXEC and

2009-05-16 18:48:41 +00:00

pci

Fall back to using configuration type 1 accesses for PCI config requests if

2009-03-24 18:10:22 +00:00

Makefile

Adjustments to make a tags file a bit more suitable to amd64.

2008-12-01 14:15:10 +00:00