3d18a9d66f
They provide relaxed-ordered atomic access semantic. Due to the FreeBSD memory model, the operations are syntaxical wrappers around the volatile accesses. The volatile qualifier is used to ensure that the access not optimized out and in turn depends on the volatile semantic as implemented by supported compilers. The motivation for adding the operation is to help people coming from other systems or knowing the C11/C++ standards where atomics have special type and require use of the special access operations. It is still the case that FreeBSD requires plain load and stores of aligned integer types to be atomic. Suggested by: jhb Reviewed by: alc, jhb Sponsored by: The FreeBSD Foundation MFC after: 1 week Differential revision: https://reviews.freebsd.org/D13534
478 lines
12 KiB
C
478 lines
12 KiB
C
/*-
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* Copyright (c) 2013 Andrew Turner <andrew@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_ATOMIC_H_
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#define _MACHINE_ATOMIC_H_
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#include <sys/atomic_common.h>
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#define isb() __asm __volatile("isb" : : : "memory")
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/*
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* Options for DMB and DSB:
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* oshld Outer Shareable, load
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* oshst Outer Shareable, store
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* osh Outer Shareable, all
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* nshld Non-shareable, load
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* nshst Non-shareable, store
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* nsh Non-shareable, all
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* ishld Inner Shareable, load
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* ishst Inner Shareable, store
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* ish Inner Shareable, all
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* ld Full system, load
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* st Full system, store
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* sy Full system, all
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*/
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#define dsb(opt) __asm __volatile("dsb " __STRING(opt) : : : "memory")
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#define dmb(opt) __asm __volatile("dmb " __STRING(opt) : : : "memory")
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#define mb() dmb(sy) /* Full system memory barrier all */
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#define wmb() dmb(st) /* Full system memory barrier store */
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#define rmb() dmb(ld) /* Full system memory barrier load */
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#define ATOMIC_OP(op, asm_op, bar, a, l) \
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static __inline void \
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atomic_##op##_##bar##32(volatile uint32_t *p, uint32_t val) \
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{ \
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uint32_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: ld"#a"xr %w0, [%2] \n" \
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" "#asm_op" %w0, %w0, %w3 \n" \
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" st"#l"xr %w1, %w0, [%2] \n" \
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" cbnz %w1, 1b \n" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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} \
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\
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static __inline void \
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atomic_##op##_##bar##64(volatile uint64_t *p, uint64_t val) \
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{ \
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uint64_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: ld"#a"xr %0, [%2] \n" \
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" "#asm_op" %0, %0, %3 \n" \
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" st"#l"xr %w1, %0, [%2] \n" \
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" cbnz %w1, 1b \n" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (val) \
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: "memory" \
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); \
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}
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#define ATOMIC(op, asm_op) \
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ATOMIC_OP(op, asm_op, , , ) \
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ATOMIC_OP(op, asm_op, acq_, a, ) \
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ATOMIC_OP(op, asm_op, rel_, , l) \
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ATOMIC(add, add)
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ATOMIC(clear, bic)
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ATOMIC(set, orr)
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ATOMIC(subtract, sub)
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#define ATOMIC_FCMPSET(bar, a, l) \
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static __inline int \
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atomic_fcmpset_##bar##32(volatile uint32_t *p, uint32_t *cmpval, \
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uint32_t newval) \
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{ \
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uint32_t tmp; \
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uint32_t _cmpval = *cmpval; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %w4, [%2] \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (_cmpval), "r" (newval) \
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: "cc", "memory" \
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); \
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*cmpval = tmp; \
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\
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return (!res); \
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} \
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\
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static __inline int \
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atomic_fcmpset_##bar##64(volatile uint64_t *p, uint64_t *cmpval, \
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uint64_t newval) \
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{ \
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uint64_t tmp; \
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uint64_t _cmpval = *cmpval; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %0, [%2] \n" \
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" cmp %0, %3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %4, [%2] \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (_cmpval), "r" (newval) \
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: "cc", "memory" \
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); \
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*cmpval = tmp; \
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\
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return (!res); \
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}
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ATOMIC_FCMPSET( , , )
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ATOMIC_FCMPSET(acq_, a, )
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ATOMIC_FCMPSET(rel_, ,l)
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#undef ATOMIC_FCMPSET
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#define ATOMIC_CMPSET(bar, a, l) \
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static __inline int \
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atomic_cmpset_##bar##32(volatile uint32_t *p, uint32_t cmpval, \
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uint32_t newval) \
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{ \
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uint32_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %w0, [%2] \n" \
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" cmp %w0, %w3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %w4, [%2] \n" \
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" cbnz %w1, 1b \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (cmpval), "r" (newval) \
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: "cc", "memory" \
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); \
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\
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return (!res); \
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} \
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\
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static __inline int \
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atomic_cmpset_##bar##64(volatile uint64_t *p, uint64_t cmpval, \
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uint64_t newval) \
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{ \
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uint64_t tmp; \
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int res; \
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\
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__asm __volatile( \
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"1: mov %w1, #1 \n" \
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" ld"#a"xr %0, [%2] \n" \
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" cmp %0, %3 \n" \
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" b.ne 2f \n" \
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" st"#l"xr %w1, %4, [%2] \n" \
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" cbnz %w1, 1b \n" \
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"2:" \
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: "=&r"(tmp), "=&r"(res) \
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: "r" (p), "r" (cmpval), "r" (newval) \
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: "cc", "memory" \
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); \
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\
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return (!res); \
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}
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ATOMIC_CMPSET( , , )
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ATOMIC_CMPSET(acq_, a, )
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ATOMIC_CMPSET(rel_, ,l)
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static __inline uint32_t
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atomic_fetchadd_32(volatile uint32_t *p, uint32_t val)
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{
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uint32_t tmp, ret;
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int res;
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__asm __volatile(
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"1: ldxr %w2, [%3] \n"
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" add %w0, %w2, %w4 \n"
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" stxr %w1, %w0, [%3] \n"
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" cbnz %w1, 1b \n"
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: "=&r"(tmp), "=&r"(res), "=&r"(ret)
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: "r" (p), "r" (val)
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: "memory"
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);
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return (ret);
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}
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static __inline uint64_t
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atomic_fetchadd_64(volatile uint64_t *p, uint64_t val)
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{
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uint64_t tmp, ret;
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int res;
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__asm __volatile(
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"1: ldxr %2, [%3] \n"
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" add %0, %2, %4 \n"
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" stxr %w1, %0, [%3] \n"
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" cbnz %w1, 1b \n"
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: "=&r"(tmp), "=&r"(res), "=&r"(ret)
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: "r" (p), "r" (val)
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: "memory"
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);
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return (ret);
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}
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static __inline uint32_t
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atomic_readandclear_32(volatile uint32_t *p)
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{
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uint32_t ret;
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int res;
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__asm __volatile(
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"1: ldxr %w1, [%2] \n"
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" stxr %w0, wzr, [%2] \n"
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" cbnz %w0, 1b \n"
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: "=&r"(res), "=&r"(ret)
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: "r" (p)
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: "memory"
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);
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return (ret);
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}
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static __inline uint64_t
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atomic_readandclear_64(volatile uint64_t *p)
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{
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uint64_t ret;
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int res;
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__asm __volatile(
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"1: ldxr %1, [%2] \n"
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" stxr %w0, xzr, [%2] \n"
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" cbnz %w0, 1b \n"
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: "=&r"(res), "=&r"(ret)
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: "r" (p)
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: "memory"
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);
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return (ret);
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}
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static __inline uint32_t
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atomic_swap_32(volatile uint32_t *p, uint32_t val)
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{
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uint32_t ret;
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int res;
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__asm __volatile(
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"1: ldxr %w0, [%2] \n"
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" stxr %w1, %w3, [%2] \n"
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" cbnz %w1, 1b \n"
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: "=&r"(ret), "=&r"(res)
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: "r" (p), "r" (val)
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: "memory"
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);
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return (ret);
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}
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static __inline uint64_t
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atomic_swap_64(volatile uint64_t *p, uint64_t val)
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{
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uint64_t ret;
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int res;
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__asm __volatile(
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"1: ldxr %0, [%2] \n"
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" stxr %w1, %3, [%2] \n"
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" cbnz %w1, 1b \n"
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: "=&r"(ret), "=&r"(res)
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: "r" (p), "r" (val)
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: "memory"
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);
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return (ret);
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}
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static __inline uint32_t
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atomic_load_acq_32(volatile uint32_t *p)
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{
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uint32_t ret;
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__asm __volatile(
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"ldar %w0, [%1] \n"
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: "=&r" (ret)
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: "r" (p)
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: "memory");
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return (ret);
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}
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static __inline uint64_t
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atomic_load_acq_64(volatile uint64_t *p)
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{
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uint64_t ret;
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__asm __volatile(
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"ldar %0, [%1] \n"
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: "=&r" (ret)
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: "r" (p)
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: "memory");
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return (ret);
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}
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static __inline void
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atomic_store_rel_32(volatile uint32_t *p, uint32_t val)
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{
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__asm __volatile(
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"stlr %w0, [%1] \n"
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:
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: "r" (val), "r" (p)
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: "memory");
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}
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static __inline void
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atomic_store_rel_64(volatile uint64_t *p, uint64_t val)
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{
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__asm __volatile(
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"stlr %0, [%1] \n"
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:
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: "r" (val), "r" (p)
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: "memory");
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}
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#define atomic_add_int atomic_add_32
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#define atomic_fcmpset_int atomic_fcmpset_32
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#define atomic_clear_int atomic_clear_32
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#define atomic_cmpset_int atomic_cmpset_32
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#define atomic_fetchadd_int atomic_fetchadd_32
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#define atomic_readandclear_int atomic_readandclear_32
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#define atomic_set_int atomic_set_32
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#define atomic_swap_int atomic_swap_32
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#define atomic_subtract_int atomic_subtract_32
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#define atomic_add_acq_int atomic_add_acq_32
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#define atomic_fcmpset_acq_int atomic_fcmpset_acq_32
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#define atomic_clear_acq_int atomic_clear_acq_32
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#define atomic_cmpset_acq_int atomic_cmpset_acq_32
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#define atomic_load_acq_int atomic_load_acq_32
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#define atomic_set_acq_int atomic_set_acq_32
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#define atomic_subtract_acq_int atomic_subtract_acq_32
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#define atomic_add_rel_int atomic_add_rel_32
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#define atomic_fcmpset_rel_int atomic_fcmpset_rel_32
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#define atomic_clear_rel_int atomic_clear_rel_32
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#define atomic_cmpset_rel_int atomic_cmpset_rel_32
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#define atomic_set_rel_int atomic_set_rel_32
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#define atomic_subtract_rel_int atomic_subtract_rel_32
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#define atomic_store_rel_int atomic_store_rel_32
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#define atomic_add_long atomic_add_64
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#define atomic_fcmpset_long atomic_fcmpset_64
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#define atomic_clear_long atomic_clear_64
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#define atomic_cmpset_long atomic_cmpset_64
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#define atomic_fetchadd_long atomic_fetchadd_64
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#define atomic_readandclear_long atomic_readandclear_64
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#define atomic_set_long atomic_set_64
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#define atomic_swap_long atomic_swap_64
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#define atomic_subtract_long atomic_subtract_64
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#define atomic_add_ptr atomic_add_64
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#define atomic_fcmpset_ptr atomic_fcmpset_64
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#define atomic_clear_ptr atomic_clear_64
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#define atomic_cmpset_ptr atomic_cmpset_64
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#define atomic_fetchadd_ptr atomic_fetchadd_64
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#define atomic_readandclear_ptr atomic_readandclear_64
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#define atomic_set_ptr atomic_set_64
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#define atomic_swap_ptr atomic_swap_64
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#define atomic_subtract_ptr atomic_subtract_64
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#define atomic_add_acq_long atomic_add_acq_64
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#define atomic_fcmpset_acq_long atomic_fcmpset_acq_64
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#define atomic_clear_acq_long atomic_clear_acq_64
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#define atomic_cmpset_acq_long atomic_cmpset_acq_64
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#define atomic_load_acq_long atomic_load_acq_64
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#define atomic_set_acq_long atomic_set_acq_64
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#define atomic_subtract_acq_long atomic_subtract_acq_64
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#define atomic_add_acq_ptr atomic_add_acq_64
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#define atomic_fcmpset_acq_ptr atomic_fcmpset_acq_64
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#define atomic_clear_acq_ptr atomic_clear_acq_64
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#define atomic_cmpset_acq_ptr atomic_cmpset_acq_64
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#define atomic_load_acq_ptr atomic_load_acq_64
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#define atomic_set_acq_ptr atomic_set_acq_64
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#define atomic_subtract_acq_ptr atomic_subtract_acq_64
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#define atomic_add_rel_long atomic_add_rel_64
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#define atomic_fcmpset_rel_long atomic_fcmpset_rel_64
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#define atomic_clear_rel_long atomic_clear_rel_64
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#define atomic_cmpset_rel_long atomic_cmpset_rel_64
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#define atomic_set_rel_long atomic_set_rel_64
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#define atomic_subtract_rel_long atomic_subtract_rel_64
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#define atomic_store_rel_long atomic_store_rel_64
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#define atomic_add_rel_ptr atomic_add_rel_64
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#define atomic_fcmpset_rel_ptr atomic_fcmpset_rel_64
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#define atomic_clear_rel_ptr atomic_clear_rel_64
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#define atomic_cmpset_rel_ptr atomic_cmpset_rel_64
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#define atomic_set_rel_ptr atomic_set_rel_64
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#define atomic_subtract_rel_ptr atomic_subtract_rel_64
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#define atomic_store_rel_ptr atomic_store_rel_64
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static __inline void
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atomic_thread_fence_acq(void)
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{
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dmb(ld);
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}
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static __inline void
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atomic_thread_fence_rel(void)
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{
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dmb(sy);
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}
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static __inline void
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atomic_thread_fence_acq_rel(void)
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{
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dmb(sy);
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}
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static __inline void
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atomic_thread_fence_seq_cst(void)
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{
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dmb(sy);
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}
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#endif /* _MACHINE_ATOMIC_H_ */
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