ca81a71128
Approved by: gallatin (mentor)
1570 lines
37 KiB
C
1570 lines
37 KiB
C
/*
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Adaptec AIC-6915 "Starfire" PCI fast ethernet driver for FreeBSD.
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* Programming manual is available from:
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* ftp.adaptec.com:/pub/BBS/userguides/aic6915_pg.pdf.
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*
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* Written by Bill Paul <wpaul@ctr.columbia.edu>
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* Department of Electical Engineering
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* Columbia University, New York City
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*/
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/*
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* The Adaptec AIC-6915 "Starfire" is a 64-bit 10/100 PCI ethernet
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* controller designed with flexibility and reducing CPU load in mind.
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* The Starfire offers high and low priority buffer queues, a
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* producer/consumer index mechanism and several different buffer
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* queue and completion queue descriptor types. Any one of a number
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* of different driver designs can be used, depending on system and
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* OS requirements. This driver makes use of type0 transmit frame
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* descriptors (since BSD fragments packets across an mbuf chain)
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* and two RX buffer queues prioritized on size (one queue for small
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* frames that will fit into a single mbuf, another with full size
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* mbuf clusters for everything else). The producer/consumer indexes
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* and completion queues are also used.
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*
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* One downside to the Starfire has to do with alignment: buffer
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* queues must be aligned on 256-byte boundaries, and receive buffers
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* must be aligned on longword boundaries. The receive buffer alignment
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* causes problems on the Alpha platform, where the packet payload
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* should be longword aligned. There is no simple way around this.
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*
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* For receive filtering, the Starfire offers 16 perfect filter slots
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* and a 512-bit hash table.
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*
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* The Starfire has no internal transceiver, relying instead on an
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* external MII-based transceiver. Accessing registers on external
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* PHYs is done through a special register map rather than with the
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* usual bitbang MDIO method.
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*
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* Acesssing the registers on the Starfire is a little tricky. The
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* Starfire has a 512K internal register space. When programmed for
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* PCI memory mapped mode, the entire register space can be accessed
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* directly. However in I/O space mode, only 256 bytes are directly
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* mapped into PCI I/O space. The other registers can be accessed
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* indirectly using the SF_INDIRECTIO_ADDR and SF_INDIRECTIO_DATA
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* registers inside the 256-byte I/O window.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/sockio.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/socket.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/bpf.h>
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#include <vm/vm.h> /* for vtophys */
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#include <vm/pmap.h> /* for vtophys */
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#include <machine/bus_pio.h>
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#include <machine/bus_memio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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/* "controller miibus0" required. See GENERIC if you get errors here. */
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#include "miibus_if.h"
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#define SF_USEIOSPACE
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#include <pci/if_sfreg.h>
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MODULE_DEPEND(sf, miibus, 1, 1, 1);
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#ifndef lint
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static const char rcsid[] =
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"$FreeBSD$";
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#endif
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static struct sf_type sf_devs[] = {
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{ AD_VENDORID, AD_DEVICEID_STARFIRE,
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"Adaptec AIC-6915 10/100BaseTX" },
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{ 0, 0, NULL }
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};
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static int sf_probe (device_t);
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static int sf_attach (device_t);
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static int sf_detach (device_t);
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static void sf_intr (void *);
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static void sf_stats_update (void *);
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static void sf_rxeof (struct sf_softc *);
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static void sf_txeof (struct sf_softc *);
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static int sf_encap (struct sf_softc *,
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struct sf_tx_bufdesc_type0 *,
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struct mbuf *);
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static void sf_start (struct ifnet *);
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static int sf_ioctl (struct ifnet *, u_long, caddr_t);
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static void sf_init (void *);
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static void sf_stop (struct sf_softc *);
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static void sf_watchdog (struct ifnet *);
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static void sf_shutdown (device_t);
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static int sf_ifmedia_upd (struct ifnet *);
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static void sf_ifmedia_sts (struct ifnet *, struct ifmediareq *);
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static void sf_reset (struct sf_softc *);
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static int sf_init_rx_ring (struct sf_softc *);
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static void sf_init_tx_ring (struct sf_softc *);
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static int sf_newbuf (struct sf_softc *,
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struct sf_rx_bufdesc_type0 *,
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struct mbuf *);
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static void sf_setmulti (struct sf_softc *);
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static int sf_setperf (struct sf_softc *, int, caddr_t);
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static int sf_sethash (struct sf_softc *, caddr_t, int);
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#ifdef notdef
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static int sf_setvlan (struct sf_softc *, int, u_int32_t);
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#endif
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static u_int8_t sf_read_eeprom (struct sf_softc *, int);
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static u_int32_t sf_calchash (caddr_t);
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static int sf_miibus_readreg (device_t, int, int);
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static int sf_miibus_writereg (device_t, int, int, int);
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static void sf_miibus_statchg (device_t);
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static u_int32_t csr_read_4 (struct sf_softc *, int);
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static void csr_write_4 (struct sf_softc *, int, u_int32_t);
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static void sf_txthresh_adjust (struct sf_softc *);
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#ifdef SF_USEIOSPACE
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#define SF_RES SYS_RES_IOPORT
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#define SF_RID SF_PCI_LOIO
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#else
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#define SF_RES SYS_RES_MEMORY
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#define SF_RID SF_PCI_LOMEM
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#endif
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static device_method_t sf_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, sf_probe),
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DEVMETHOD(device_attach, sf_attach),
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DEVMETHOD(device_detach, sf_detach),
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DEVMETHOD(device_shutdown, sf_shutdown),
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/* bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_driver_added, bus_generic_driver_added),
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/* MII interface */
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DEVMETHOD(miibus_readreg, sf_miibus_readreg),
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DEVMETHOD(miibus_writereg, sf_miibus_writereg),
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DEVMETHOD(miibus_statchg, sf_miibus_statchg),
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{ 0, 0 }
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};
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static driver_t sf_driver = {
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"sf",
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sf_methods,
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sizeof(struct sf_softc),
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};
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static devclass_t sf_devclass;
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DRIVER_MODULE(if_sf, pci, sf_driver, sf_devclass, 0, 0);
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DRIVER_MODULE(miibus, sf, miibus_driver, miibus_devclass, 0, 0);
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#define SF_SETBIT(sc, reg, x) \
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csr_write_4(sc, reg, csr_read_4(sc, reg) | x)
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#define SF_CLRBIT(sc, reg, x) \
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csr_write_4(sc, reg, csr_read_4(sc, reg) & ~x)
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static u_int32_t
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csr_read_4(sc, reg)
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struct sf_softc *sc;
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int reg;
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{
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u_int32_t val;
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#ifdef SF_USEIOSPACE
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CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
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val = CSR_READ_4(sc, SF_INDIRECTIO_DATA);
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#else
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val = CSR_READ_4(sc, (reg + SF_RMAP_INTREG_BASE));
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#endif
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return(val);
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}
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static u_int8_t
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sf_read_eeprom(sc, reg)
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struct sf_softc *sc;
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int reg;
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{
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u_int8_t val;
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val = (csr_read_4(sc, SF_EEADDR_BASE +
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(reg & 0xFFFFFFFC)) >> (8 * (reg & 3))) & 0xFF;
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return(val);
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}
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static void
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csr_write_4(sc, reg, val)
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struct sf_softc *sc;
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int reg;
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u_int32_t val;
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{
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#ifdef SF_USEIOSPACE
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CSR_WRITE_4(sc, SF_INDIRECTIO_ADDR, reg + SF_RMAP_INTREG_BASE);
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CSR_WRITE_4(sc, SF_INDIRECTIO_DATA, val);
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#else
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CSR_WRITE_4(sc, (reg + SF_RMAP_INTREG_BASE), val);
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#endif
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return;
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}
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static u_int32_t
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sf_calchash(addr)
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caddr_t addr;
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{
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u_int32_t crc, carry;
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int i, j;
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u_int8_t c;
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/* Compute CRC for the address value. */
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crc = 0xFFFFFFFF; /* initial value */
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for (i = 0; i < 6; i++) {
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c = *(addr + i);
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for (j = 0; j < 8; j++) {
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carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
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crc <<= 1;
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c >>= 1;
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if (carry)
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crc = (crc ^ 0x04c11db6) | carry;
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}
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}
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/* return the filter bit position */
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return(crc >> 23 & 0x1FF);
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}
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/*
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* Copy the address 'mac' into the perfect RX filter entry at
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* offset 'idx.' The perfect filter only has 16 entries so do
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* some sanity tests.
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*/
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static int
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sf_setperf(sc, idx, mac)
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struct sf_softc *sc;
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int idx;
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caddr_t mac;
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{
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u_int16_t *p;
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if (idx < 0 || idx > SF_RXFILT_PERFECT_CNT)
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return(EINVAL);
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if (mac == NULL)
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return(EINVAL);
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p = (u_int16_t *)mac;
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csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
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(idx * SF_RXFILT_PERFECT_SKIP), htons(p[2]));
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csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
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(idx * SF_RXFILT_PERFECT_SKIP) + 4, htons(p[1]));
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csr_write_4(sc, SF_RXFILT_PERFECT_BASE +
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(idx * SF_RXFILT_PERFECT_SKIP) + 8, htons(p[0]));
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return(0);
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}
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/*
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* Set the bit in the 512-bit hash table that corresponds to the
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* specified mac address 'mac.' If 'prio' is nonzero, update the
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* priority hash table instead of the filter hash table.
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*/
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static int
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sf_sethash(sc, mac, prio)
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struct sf_softc *sc;
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caddr_t mac;
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int prio;
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{
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u_int32_t h = 0;
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if (mac == NULL)
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return(EINVAL);
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h = sf_calchash(mac);
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if (prio) {
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SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_PRIOOFF +
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(SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
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} else {
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SF_SETBIT(sc, SF_RXFILT_HASH_BASE + SF_RXFILT_HASH_ADDROFF +
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(SF_RXFILT_HASH_SKIP * (h >> 4)), (1 << (h & 0xF)));
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}
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return(0);
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}
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#ifdef notdef
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/*
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* Set a VLAN tag in the receive filter.
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*/
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static int
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sf_setvlan(sc, idx, vlan)
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struct sf_softc *sc;
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int idx;
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u_int32_t vlan;
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{
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if (idx < 0 || idx >> SF_RXFILT_HASH_CNT)
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return(EINVAL);
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csr_write_4(sc, SF_RXFILT_HASH_BASE +
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(idx * SF_RXFILT_HASH_SKIP) + SF_RXFILT_HASH_VLANOFF, vlan);
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return(0);
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}
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#endif
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static int
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sf_miibus_readreg(dev, phy, reg)
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device_t dev;
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int phy, reg;
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{
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struct sf_softc *sc;
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int i;
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u_int32_t val = 0;
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sc = device_get_softc(dev);
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for (i = 0; i < SF_TIMEOUT; i++) {
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val = csr_read_4(sc, SF_PHY_REG(phy, reg));
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if (val & SF_MII_DATAVALID)
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break;
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}
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if (i == SF_TIMEOUT)
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return(0);
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if ((val & 0x0000FFFF) == 0xFFFF)
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return(0);
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return(val & 0x0000FFFF);
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}
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static int
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sf_miibus_writereg(dev, phy, reg, val)
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device_t dev;
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int phy, reg, val;
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{
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struct sf_softc *sc;
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int i;
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int busy;
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sc = device_get_softc(dev);
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csr_write_4(sc, SF_PHY_REG(phy, reg), val);
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for (i = 0; i < SF_TIMEOUT; i++) {
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busy = csr_read_4(sc, SF_PHY_REG(phy, reg));
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if (!(busy & SF_MII_BUSY))
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break;
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}
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return(0);
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}
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static void
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sf_miibus_statchg(dev)
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device_t dev;
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{
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struct sf_softc *sc;
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struct mii_data *mii;
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sc = device_get_softc(dev);
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mii = device_get_softc(sc->sf_miibus);
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if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
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SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
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csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_FDX);
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} else {
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SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_FULLDUPLEX);
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csr_write_4(sc, SF_BKTOBKIPG, SF_IPGT_HDX);
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}
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return;
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}
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static void
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sf_setmulti(sc)
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struct sf_softc *sc;
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{
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struct ifnet *ifp;
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int i;
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struct ifmultiaddr *ifma;
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u_int8_t dummy[] = { 0, 0, 0, 0, 0, 0 };
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ifp = &sc->arpcom.ac_if;
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/* First zot all the existing filters. */
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for (i = 1; i < SF_RXFILT_PERFECT_CNT; i++)
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sf_setperf(sc, i, (char *)&dummy);
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for (i = SF_RXFILT_HASH_BASE;
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i < (SF_RXFILT_HASH_MAX + 1); i += 4)
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csr_write_4(sc, i, 0);
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SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
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/* Now program new ones. */
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if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
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SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_ALLMULTI);
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} else {
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i = 1;
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TAILQ_FOREACH_REVERSE(ifma, &ifp->if_multiaddrs, ifmultihead, ifma_link) {
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if (ifma->ifma_addr->sa_family != AF_LINK)
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continue;
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/*
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* Program the first 15 multicast groups
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* into the perfect filter. For all others,
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* use the hash table.
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*/
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if (i < SF_RXFILT_PERFECT_CNT) {
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sf_setperf(sc, i,
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LLADDR((struct sockaddr_dl *)ifma->ifma_addr));
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i++;
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continue;
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}
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sf_sethash(sc,
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LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 0);
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}
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}
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return;
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}
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/*
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* Set media options.
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*/
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static int
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sf_ifmedia_upd(ifp)
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struct ifnet *ifp;
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{
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struct sf_softc *sc;
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struct mii_data *mii;
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sc = ifp->if_softc;
|
|
mii = device_get_softc(sc->sf_miibus);
|
|
sc->sf_link = 0;
|
|
if (mii->mii_instance) {
|
|
struct mii_softc *miisc;
|
|
LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
|
|
mii_phy_reset(miisc);
|
|
}
|
|
mii_mediachg(mii);
|
|
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* Report current media status.
|
|
*/
|
|
static void
|
|
sf_ifmedia_sts(ifp, ifmr)
|
|
struct ifnet *ifp;
|
|
struct ifmediareq *ifmr;
|
|
{
|
|
struct sf_softc *sc;
|
|
struct mii_data *mii;
|
|
|
|
sc = ifp->if_softc;
|
|
mii = device_get_softc(sc->sf_miibus);
|
|
|
|
mii_pollstat(mii);
|
|
ifmr->ifm_active = mii->mii_media_active;
|
|
ifmr->ifm_status = mii->mii_media_status;
|
|
|
|
return;
|
|
}
|
|
|
|
static int
|
|
sf_ioctl(ifp, command, data)
|
|
struct ifnet *ifp;
|
|
u_long command;
|
|
caddr_t data;
|
|
{
|
|
struct sf_softc *sc = ifp->if_softc;
|
|
struct ifreq *ifr = (struct ifreq *) data;
|
|
struct mii_data *mii;
|
|
int error = 0;
|
|
|
|
SF_LOCK(sc);
|
|
|
|
switch(command) {
|
|
case SIOCSIFADDR:
|
|
case SIOCGIFADDR:
|
|
case SIOCSIFMTU:
|
|
error = ether_ioctl(ifp, command, data);
|
|
break;
|
|
case SIOCSIFFLAGS:
|
|
if (ifp->if_flags & IFF_UP) {
|
|
if (ifp->if_flags & IFF_RUNNING &&
|
|
ifp->if_flags & IFF_PROMISC &&
|
|
!(sc->sf_if_flags & IFF_PROMISC)) {
|
|
SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
|
|
} else if (ifp->if_flags & IFF_RUNNING &&
|
|
!(ifp->if_flags & IFF_PROMISC) &&
|
|
sc->sf_if_flags & IFF_PROMISC) {
|
|
SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
|
|
} else if (!(ifp->if_flags & IFF_RUNNING))
|
|
sf_init(sc);
|
|
} else {
|
|
if (ifp->if_flags & IFF_RUNNING)
|
|
sf_stop(sc);
|
|
}
|
|
sc->sf_if_flags = ifp->if_flags;
|
|
error = 0;
|
|
break;
|
|
case SIOCADDMULTI:
|
|
case SIOCDELMULTI:
|
|
sf_setmulti(sc);
|
|
error = 0;
|
|
break;
|
|
case SIOCGIFMEDIA:
|
|
case SIOCSIFMEDIA:
|
|
mii = device_get_softc(sc->sf_miibus);
|
|
error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
|
|
break;
|
|
default:
|
|
error = EINVAL;
|
|
break;
|
|
}
|
|
|
|
SF_UNLOCK(sc);
|
|
|
|
return(error);
|
|
}
|
|
|
|
static void
|
|
sf_reset(sc)
|
|
struct sf_softc *sc;
|
|
{
|
|
register int i;
|
|
|
|
csr_write_4(sc, SF_GEN_ETH_CTL, 0);
|
|
SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
|
|
DELAY(1000);
|
|
SF_CLRBIT(sc, SF_MACCFG_1, SF_MACCFG1_SOFTRESET);
|
|
|
|
SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_RESET);
|
|
|
|
for (i = 0; i < SF_TIMEOUT; i++) {
|
|
DELAY(10);
|
|
if (!(csr_read_4(sc, SF_PCI_DEVCFG) & SF_PCIDEVCFG_RESET))
|
|
break;
|
|
}
|
|
|
|
if (i == SF_TIMEOUT)
|
|
printf("sf%d: reset never completed!\n", sc->sf_unit);
|
|
|
|
/* Wait a little while for the chip to get its brains in order. */
|
|
DELAY(1000);
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Probe for an Adaptec AIC-6915 chip. Check the PCI vendor and device
|
|
* IDs against our list and return a device name if we find a match.
|
|
* We also check the subsystem ID so that we can identify exactly which
|
|
* NIC has been found, if possible.
|
|
*/
|
|
static int
|
|
sf_probe(dev)
|
|
device_t dev;
|
|
{
|
|
struct sf_type *t;
|
|
|
|
t = sf_devs;
|
|
|
|
while(t->sf_name != NULL) {
|
|
if ((pci_get_vendor(dev) == t->sf_vid) &&
|
|
(pci_get_device(dev) == t->sf_did)) {
|
|
switch((pci_read_config(dev,
|
|
SF_PCI_SUBVEN_ID, 4) >> 16) & 0xFFFF) {
|
|
case AD_SUBSYSID_62011_REV0:
|
|
case AD_SUBSYSID_62011_REV1:
|
|
device_set_desc(dev,
|
|
"Adaptec ANA-62011 10/100BaseTX");
|
|
return(0);
|
|
break;
|
|
case AD_SUBSYSID_62022:
|
|
device_set_desc(dev,
|
|
"Adaptec ANA-62022 10/100BaseTX");
|
|
return(0);
|
|
break;
|
|
case AD_SUBSYSID_62044_REV0:
|
|
case AD_SUBSYSID_62044_REV1:
|
|
device_set_desc(dev,
|
|
"Adaptec ANA-62044 10/100BaseTX");
|
|
return(0);
|
|
break;
|
|
case AD_SUBSYSID_62020:
|
|
device_set_desc(dev,
|
|
"Adaptec ANA-62020 10/100BaseFX");
|
|
return(0);
|
|
break;
|
|
case AD_SUBSYSID_69011:
|
|
device_set_desc(dev,
|
|
"Adaptec ANA-69011 10/100BaseTX");
|
|
return(0);
|
|
break;
|
|
default:
|
|
device_set_desc(dev, t->sf_name);
|
|
return(0);
|
|
break;
|
|
}
|
|
}
|
|
t++;
|
|
}
|
|
|
|
return(ENXIO);
|
|
}
|
|
|
|
/*
|
|
* Attach the interface. Allocate softc structures, do ifmedia
|
|
* setup and ethernet/BPF attach.
|
|
*/
|
|
static int
|
|
sf_attach(dev)
|
|
device_t dev;
|
|
{
|
|
int i;
|
|
u_int32_t command;
|
|
struct sf_softc *sc;
|
|
struct ifnet *ifp;
|
|
int unit, rid, error = 0;
|
|
|
|
sc = device_get_softc(dev);
|
|
unit = device_get_unit(dev);
|
|
bzero(sc, sizeof(struct sf_softc));
|
|
|
|
mtx_init(&sc->sf_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
|
|
MTX_DEF | MTX_RECURSE);
|
|
SF_LOCK(sc);
|
|
/*
|
|
* Handle power management nonsense.
|
|
*/
|
|
if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
|
|
u_int32_t iobase, membase, irq;
|
|
|
|
/* Save important PCI config data. */
|
|
iobase = pci_read_config(dev, SF_PCI_LOIO, 4);
|
|
membase = pci_read_config(dev, SF_PCI_LOMEM, 4);
|
|
irq = pci_read_config(dev, SF_PCI_INTLINE, 4);
|
|
|
|
/* Reset the power state. */
|
|
printf("sf%d: chip is in D%d power mode "
|
|
"-- setting to D0\n", unit,
|
|
pci_get_powerstate(dev));
|
|
pci_set_powerstate(dev, PCI_POWERSTATE_D0);
|
|
|
|
/* Restore PCI config data. */
|
|
pci_write_config(dev, SF_PCI_LOIO, iobase, 4);
|
|
pci_write_config(dev, SF_PCI_LOMEM, membase, 4);
|
|
pci_write_config(dev, SF_PCI_INTLINE, irq, 4);
|
|
}
|
|
|
|
/*
|
|
* Map control/status registers.
|
|
*/
|
|
pci_enable_busmaster(dev);
|
|
pci_enable_io(dev, SYS_RES_IOPORT);
|
|
pci_enable_io(dev, SYS_RES_MEMORY);
|
|
command = pci_read_config(dev, PCIR_COMMAND, 4);
|
|
|
|
#ifdef SF_USEIOSPACE
|
|
if (!(command & PCIM_CMD_PORTEN)) {
|
|
printf("sf%d: failed to enable I/O ports!\n", unit);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
#else
|
|
if (!(command & PCIM_CMD_MEMEN)) {
|
|
printf("sf%d: failed to enable memory mapping!\n", unit);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
#endif
|
|
|
|
rid = SF_RID;
|
|
sc->sf_res = bus_alloc_resource(dev, SF_RES, &rid,
|
|
0, ~0, 1, RF_ACTIVE);
|
|
|
|
if (sc->sf_res == NULL) {
|
|
printf ("sf%d: couldn't map ports\n", unit);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
sc->sf_btag = rman_get_bustag(sc->sf_res);
|
|
sc->sf_bhandle = rman_get_bushandle(sc->sf_res);
|
|
|
|
/* Allocate interrupt */
|
|
rid = 0;
|
|
sc->sf_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
|
|
RF_SHAREABLE | RF_ACTIVE);
|
|
|
|
if (sc->sf_irq == NULL) {
|
|
printf("sf%d: couldn't map interrupt\n", unit);
|
|
bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
error = bus_setup_intr(dev, sc->sf_irq, INTR_TYPE_NET,
|
|
sf_intr, sc, &sc->sf_intrhand);
|
|
|
|
if (error) {
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_res);
|
|
bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
|
|
printf("sf%d: couldn't set up irq\n", unit);
|
|
goto fail;
|
|
}
|
|
|
|
callout_handle_init(&sc->sf_stat_ch);
|
|
/* Reset the adapter. */
|
|
sf_reset(sc);
|
|
|
|
/*
|
|
* Get station address from the EEPROM.
|
|
*/
|
|
for (i = 0; i < ETHER_ADDR_LEN; i++)
|
|
sc->arpcom.ac_enaddr[i] =
|
|
sf_read_eeprom(sc, SF_EE_NODEADDR + ETHER_ADDR_LEN - i);
|
|
|
|
/*
|
|
* An Adaptec chip was detected. Inform the world.
|
|
*/
|
|
printf("sf%d: Ethernet address: %6D\n", unit,
|
|
sc->arpcom.ac_enaddr, ":");
|
|
|
|
sc->sf_unit = unit;
|
|
|
|
/* Allocate the descriptor queues. */
|
|
sc->sf_ldata = contigmalloc(sizeof(struct sf_list_data), M_DEVBUF,
|
|
M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0);
|
|
|
|
if (sc->sf_ldata == NULL) {
|
|
printf("sf%d: no memory for list buffers!\n", unit);
|
|
bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
|
|
bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
bzero(sc->sf_ldata, sizeof(struct sf_list_data));
|
|
|
|
/* Do MII setup. */
|
|
if (mii_phy_probe(dev, &sc->sf_miibus,
|
|
sf_ifmedia_upd, sf_ifmedia_sts)) {
|
|
printf("sf%d: MII without any phy!\n", sc->sf_unit);
|
|
contigfree(sc->sf_ldata,sizeof(struct sf_list_data),M_DEVBUF);
|
|
bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
|
|
bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
|
|
error = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
ifp->if_softc = sc;
|
|
ifp->if_unit = unit;
|
|
ifp->if_name = "sf";
|
|
ifp->if_mtu = ETHERMTU;
|
|
ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
|
|
ifp->if_ioctl = sf_ioctl;
|
|
ifp->if_output = ether_output;
|
|
ifp->if_start = sf_start;
|
|
ifp->if_watchdog = sf_watchdog;
|
|
ifp->if_init = sf_init;
|
|
ifp->if_baudrate = 10000000;
|
|
ifp->if_snd.ifq_maxlen = SF_TX_DLIST_CNT - 1;
|
|
|
|
/*
|
|
* Call MI attach routine.
|
|
*/
|
|
ether_ifattach(ifp, ETHER_BPF_SUPPORTED);
|
|
SF_UNLOCK(sc);
|
|
return(0);
|
|
|
|
fail:
|
|
SF_UNLOCK(sc);
|
|
mtx_destroy(&sc->sf_mtx);
|
|
return(error);
|
|
}
|
|
|
|
static int
|
|
sf_detach(dev)
|
|
device_t dev;
|
|
{
|
|
struct sf_softc *sc;
|
|
struct ifnet *ifp;
|
|
|
|
sc = device_get_softc(dev);
|
|
SF_LOCK(sc);
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
ether_ifdetach(ifp, ETHER_BPF_SUPPORTED);
|
|
sf_stop(sc);
|
|
|
|
bus_generic_detach(dev);
|
|
device_delete_child(dev, sc->sf_miibus);
|
|
|
|
bus_teardown_intr(dev, sc->sf_irq, sc->sf_intrhand);
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sf_irq);
|
|
bus_release_resource(dev, SF_RES, SF_RID, sc->sf_res);
|
|
|
|
contigfree(sc->sf_ldata, sizeof(struct sf_list_data), M_DEVBUF);
|
|
|
|
SF_UNLOCK(sc);
|
|
mtx_destroy(&sc->sf_mtx);
|
|
|
|
return(0);
|
|
}
|
|
|
|
static int
|
|
sf_init_rx_ring(sc)
|
|
struct sf_softc *sc;
|
|
{
|
|
struct sf_list_data *ld;
|
|
int i;
|
|
|
|
ld = sc->sf_ldata;
|
|
|
|
bzero((char *)ld->sf_rx_dlist_big,
|
|
sizeof(struct sf_rx_bufdesc_type0) * SF_RX_DLIST_CNT);
|
|
bzero((char *)ld->sf_rx_clist,
|
|
sizeof(struct sf_rx_cmpdesc_type3) * SF_RX_CLIST_CNT);
|
|
|
|
for (i = 0; i < SF_RX_DLIST_CNT; i++) {
|
|
if (sf_newbuf(sc, &ld->sf_rx_dlist_big[i], NULL) == ENOBUFS)
|
|
return(ENOBUFS);
|
|
}
|
|
|
|
return(0);
|
|
}
|
|
|
|
static void
|
|
sf_init_tx_ring(sc)
|
|
struct sf_softc *sc;
|
|
{
|
|
struct sf_list_data *ld;
|
|
int i;
|
|
|
|
ld = sc->sf_ldata;
|
|
|
|
bzero((char *)ld->sf_tx_dlist,
|
|
sizeof(struct sf_tx_bufdesc_type0) * SF_TX_DLIST_CNT);
|
|
bzero((char *)ld->sf_tx_clist,
|
|
sizeof(struct sf_tx_cmpdesc_type0) * SF_TX_CLIST_CNT);
|
|
|
|
for (i = 0; i < SF_TX_DLIST_CNT; i++)
|
|
ld->sf_tx_dlist[i].sf_id = SF_TX_BUFDESC_ID;
|
|
for (i = 0; i < SF_TX_CLIST_CNT; i++)
|
|
ld->sf_tx_clist[i].sf_type = SF_TXCMPTYPE_TX;
|
|
|
|
ld->sf_tx_dlist[SF_TX_DLIST_CNT - 1].sf_end = 1;
|
|
sc->sf_tx_cnt = 0;
|
|
|
|
return;
|
|
}
|
|
|
|
static int
|
|
sf_newbuf(sc, c, m)
|
|
struct sf_softc *sc;
|
|
struct sf_rx_bufdesc_type0 *c;
|
|
struct mbuf *m;
|
|
{
|
|
struct mbuf *m_new = NULL;
|
|
|
|
if (m == NULL) {
|
|
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
|
|
if (m_new == NULL)
|
|
return(ENOBUFS);
|
|
|
|
MCLGET(m_new, M_DONTWAIT);
|
|
if (!(m_new->m_flags & M_EXT)) {
|
|
m_freem(m_new);
|
|
return(ENOBUFS);
|
|
}
|
|
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
|
|
} else {
|
|
m_new = m;
|
|
m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
|
|
m_new->m_data = m_new->m_ext.ext_buf;
|
|
}
|
|
|
|
m_adj(m_new, sizeof(u_int64_t));
|
|
|
|
c->sf_mbuf = m_new;
|
|
c->sf_addrlo = SF_RX_HOSTADDR(vtophys(mtod(m_new, caddr_t)));
|
|
c->sf_valid = 1;
|
|
|
|
return(0);
|
|
}
|
|
|
|
/*
|
|
* The starfire is programmed to use 'normal' mode for packet reception,
|
|
* which means we use the consumer/producer model for both the buffer
|
|
* descriptor queue and the completion descriptor queue. The only problem
|
|
* with this is that it involves a lot of register accesses: we have to
|
|
* read the RX completion consumer and producer indexes and the RX buffer
|
|
* producer index, plus the RX completion consumer and RX buffer producer
|
|
* indexes have to be updated. It would have been easier if Adaptec had
|
|
* put each index in a separate register, especially given that the damn
|
|
* NIC has a 512K register space.
|
|
*
|
|
* In spite of all the lovely features that Adaptec crammed into the 6915,
|
|
* it is marred by one truly stupid design flaw, which is that receive
|
|
* buffer addresses must be aligned on a longword boundary. This forces
|
|
* the packet payload to be unaligned, which is suboptimal on the x86 and
|
|
* completely unuseable on the Alpha. Our only recourse is to copy received
|
|
* packets into properly aligned buffers before handing them off.
|
|
*/
|
|
|
|
static void
|
|
sf_rxeof(sc)
|
|
struct sf_softc *sc;
|
|
{
|
|
struct ether_header *eh;
|
|
struct mbuf *m;
|
|
struct ifnet *ifp;
|
|
struct sf_rx_bufdesc_type0 *desc;
|
|
struct sf_rx_cmpdesc_type3 *cur_rx;
|
|
u_int32_t rxcons, rxprod;
|
|
int cmpprodidx, cmpconsidx, bufprodidx;
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
rxcons = csr_read_4(sc, SF_CQ_CONSIDX);
|
|
rxprod = csr_read_4(sc, SF_RXDQ_PTR_Q1);
|
|
cmpprodidx = SF_IDX_LO(csr_read_4(sc, SF_CQ_PRODIDX));
|
|
cmpconsidx = SF_IDX_LO(rxcons);
|
|
bufprodidx = SF_IDX_LO(rxprod);
|
|
|
|
while (cmpconsidx != cmpprodidx) {
|
|
struct mbuf *m0;
|
|
|
|
cur_rx = &sc->sf_ldata->sf_rx_clist[cmpconsidx];
|
|
desc = &sc->sf_ldata->sf_rx_dlist_big[cur_rx->sf_endidx];
|
|
m = desc->sf_mbuf;
|
|
SF_INC(cmpconsidx, SF_RX_CLIST_CNT);
|
|
SF_INC(bufprodidx, SF_RX_DLIST_CNT);
|
|
|
|
if (!(cur_rx->sf_status1 & SF_RXSTAT1_OK)) {
|
|
ifp->if_ierrors++;
|
|
sf_newbuf(sc, desc, m);
|
|
continue;
|
|
}
|
|
|
|
m0 = m_devget(mtod(m, char *), cur_rx->sf_len, ETHER_ALIGN,
|
|
ifp, NULL);
|
|
sf_newbuf(sc, desc, m);
|
|
if (m0 == NULL) {
|
|
ifp->if_ierrors++;
|
|
continue;
|
|
}
|
|
m = m0;
|
|
|
|
eh = mtod(m, struct ether_header *);
|
|
ifp->if_ipackets++;
|
|
|
|
/* Remove header from mbuf and pass it on. */
|
|
m_adj(m, sizeof(struct ether_header));
|
|
ether_input(ifp, eh, m);
|
|
}
|
|
|
|
csr_write_4(sc, SF_CQ_CONSIDX,
|
|
(rxcons & ~SF_CQ_CONSIDX_RXQ1) | cmpconsidx);
|
|
csr_write_4(sc, SF_RXDQ_PTR_Q1,
|
|
(rxprod & ~SF_RXDQ_PRODIDX) | bufprodidx);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Read the transmit status from the completion queue and release
|
|
* mbufs. Note that the buffer descriptor index in the completion
|
|
* descriptor is an offset from the start of the transmit buffer
|
|
* descriptor list in bytes. This is important because the manual
|
|
* gives the impression that it should match the producer/consumer
|
|
* index, which is the offset in 8 byte blocks.
|
|
*/
|
|
static void
|
|
sf_txeof(sc)
|
|
struct sf_softc *sc;
|
|
{
|
|
int txcons, cmpprodidx, cmpconsidx;
|
|
struct sf_tx_cmpdesc_type1 *cur_cmp;
|
|
struct sf_tx_bufdesc_type0 *cur_tx;
|
|
struct ifnet *ifp;
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
txcons = csr_read_4(sc, SF_CQ_CONSIDX);
|
|
cmpprodidx = SF_IDX_HI(csr_read_4(sc, SF_CQ_PRODIDX));
|
|
cmpconsidx = SF_IDX_HI(txcons);
|
|
|
|
while (cmpconsidx != cmpprodidx) {
|
|
cur_cmp = &sc->sf_ldata->sf_tx_clist[cmpconsidx];
|
|
cur_tx = &sc->sf_ldata->sf_tx_dlist[cur_cmp->sf_index >> 7];
|
|
|
|
if (cur_cmp->sf_txstat & SF_TXSTAT_TX_OK)
|
|
ifp->if_opackets++;
|
|
else {
|
|
if (cur_cmp->sf_txstat & SF_TXSTAT_TX_UNDERRUN)
|
|
sf_txthresh_adjust(sc);
|
|
ifp->if_oerrors++;
|
|
}
|
|
|
|
sc->sf_tx_cnt--;
|
|
if (cur_tx->sf_mbuf != NULL) {
|
|
m_freem(cur_tx->sf_mbuf);
|
|
cur_tx->sf_mbuf = NULL;
|
|
} else
|
|
break;
|
|
SF_INC(cmpconsidx, SF_TX_CLIST_CNT);
|
|
}
|
|
|
|
ifp->if_timer = 0;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
csr_write_4(sc, SF_CQ_CONSIDX,
|
|
(txcons & ~SF_CQ_CONSIDX_TXQ) |
|
|
((cmpconsidx << 16) & 0xFFFF0000));
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
sf_txthresh_adjust(sc)
|
|
struct sf_softc *sc;
|
|
{
|
|
u_int32_t txfctl;
|
|
u_int8_t txthresh;
|
|
|
|
txfctl = csr_read_4(sc, SF_TX_FRAMCTL);
|
|
txthresh = txfctl & SF_TXFRMCTL_TXTHRESH;
|
|
if (txthresh < 0xFF) {
|
|
txthresh++;
|
|
txfctl &= ~SF_TXFRMCTL_TXTHRESH;
|
|
txfctl |= txthresh;
|
|
#ifdef DIAGNOSTIC
|
|
printf("sf%d: tx underrun, increasing "
|
|
"tx threshold to %d bytes\n",
|
|
sc->sf_unit, txthresh * 4);
|
|
#endif
|
|
csr_write_4(sc, SF_TX_FRAMCTL, txfctl);
|
|
}
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
sf_intr(arg)
|
|
void *arg;
|
|
{
|
|
struct sf_softc *sc;
|
|
struct ifnet *ifp;
|
|
u_int32_t status;
|
|
|
|
sc = arg;
|
|
SF_LOCK(sc);
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
if (!(csr_read_4(sc, SF_ISR_SHADOW) & SF_ISR_PCIINT_ASSERTED)) {
|
|
SF_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
/* Disable interrupts. */
|
|
csr_write_4(sc, SF_IMR, 0x00000000);
|
|
|
|
for (;;) {
|
|
status = csr_read_4(sc, SF_ISR);
|
|
if (status)
|
|
csr_write_4(sc, SF_ISR, status);
|
|
|
|
if (!(status & SF_INTRS))
|
|
break;
|
|
|
|
if (status & SF_ISR_RXDQ1_DMADONE)
|
|
sf_rxeof(sc);
|
|
|
|
if (status & SF_ISR_TX_TXDONE ||
|
|
status & SF_ISR_TX_DMADONE ||
|
|
status & SF_ISR_TX_QUEUEDONE)
|
|
sf_txeof(sc);
|
|
|
|
if (status & SF_ISR_TX_LOFIFO)
|
|
sf_txthresh_adjust(sc);
|
|
|
|
if (status & SF_ISR_ABNORMALINTR) {
|
|
if (status & SF_ISR_STATSOFLOW) {
|
|
untimeout(sf_stats_update, sc,
|
|
sc->sf_stat_ch);
|
|
sf_stats_update(sc);
|
|
} else
|
|
sf_init(sc);
|
|
}
|
|
}
|
|
|
|
/* Re-enable interrupts. */
|
|
csr_write_4(sc, SF_IMR, SF_INTRS);
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
sf_start(ifp);
|
|
|
|
SF_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
static void
|
|
sf_init(xsc)
|
|
void *xsc;
|
|
{
|
|
struct sf_softc *sc;
|
|
struct ifnet *ifp;
|
|
struct mii_data *mii;
|
|
int i;
|
|
|
|
sc = xsc;
|
|
SF_LOCK(sc);
|
|
ifp = &sc->arpcom.ac_if;
|
|
mii = device_get_softc(sc->sf_miibus);
|
|
|
|
sf_stop(sc);
|
|
sf_reset(sc);
|
|
|
|
/* Init all the receive filter registers */
|
|
for (i = SF_RXFILT_PERFECT_BASE;
|
|
i < (SF_RXFILT_HASH_MAX + 1); i += 4)
|
|
csr_write_4(sc, i, 0);
|
|
|
|
/* Empty stats counter registers. */
|
|
for (i = 0; i < sizeof(struct sf_stats)/sizeof(u_int32_t); i++)
|
|
csr_write_4(sc, SF_STATS_BASE +
|
|
(i + sizeof(u_int32_t)), 0);
|
|
|
|
/* Init our MAC address */
|
|
csr_write_4(sc, SF_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0]));
|
|
csr_write_4(sc, SF_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4]));
|
|
sf_setperf(sc, 0, (caddr_t)&sc->arpcom.ac_enaddr);
|
|
|
|
if (sf_init_rx_ring(sc) == ENOBUFS) {
|
|
printf("sf%d: initialization failed: no "
|
|
"memory for rx buffers\n", sc->sf_unit);
|
|
SF_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
sf_init_tx_ring(sc);
|
|
|
|
csr_write_4(sc, SF_RXFILT, SF_PERFMODE_NORMAL|SF_HASHMODE_WITHVLAN);
|
|
|
|
/* If we want promiscuous mode, set the allframes bit. */
|
|
if (ifp->if_flags & IFF_PROMISC) {
|
|
SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
|
|
} else {
|
|
SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_PROMISC);
|
|
}
|
|
|
|
if (ifp->if_flags & IFF_BROADCAST) {
|
|
SF_SETBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
|
|
} else {
|
|
SF_CLRBIT(sc, SF_RXFILT, SF_RXFILT_BROAD);
|
|
}
|
|
|
|
/*
|
|
* Load the multicast filter.
|
|
*/
|
|
sf_setmulti(sc);
|
|
|
|
/* Init the completion queue indexes */
|
|
csr_write_4(sc, SF_CQ_CONSIDX, 0);
|
|
csr_write_4(sc, SF_CQ_PRODIDX, 0);
|
|
|
|
/* Init the RX completion queue */
|
|
csr_write_4(sc, SF_RXCQ_CTL_1,
|
|
vtophys(sc->sf_ldata->sf_rx_clist) & SF_RXCQ_ADDR);
|
|
SF_SETBIT(sc, SF_RXCQ_CTL_1, SF_RXCQTYPE_3);
|
|
|
|
/* Init RX DMA control. */
|
|
SF_SETBIT(sc, SF_RXDMA_CTL, SF_RXDMA_REPORTBADPKTS);
|
|
|
|
/* Init the RX buffer descriptor queue. */
|
|
csr_write_4(sc, SF_RXDQ_ADDR_Q1,
|
|
vtophys(sc->sf_ldata->sf_rx_dlist_big));
|
|
csr_write_4(sc, SF_RXDQ_CTL_1, (MCLBYTES << 16) | SF_DESCSPACE_16BYTES);
|
|
csr_write_4(sc, SF_RXDQ_PTR_Q1, SF_RX_DLIST_CNT - 1);
|
|
|
|
/* Init the TX completion queue */
|
|
csr_write_4(sc, SF_TXCQ_CTL,
|
|
vtophys(sc->sf_ldata->sf_tx_clist) & SF_RXCQ_ADDR);
|
|
|
|
/* Init the TX buffer descriptor queue. */
|
|
csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO,
|
|
vtophys(sc->sf_ldata->sf_tx_dlist));
|
|
SF_SETBIT(sc, SF_TX_FRAMCTL, SF_TXFRMCTL_CPLAFTERTX);
|
|
csr_write_4(sc, SF_TXDQ_CTL,
|
|
SF_TXBUFDESC_TYPE0|SF_TXMINSPACE_128BYTES|SF_TXSKIPLEN_8BYTES);
|
|
SF_SETBIT(sc, SF_TXDQ_CTL, SF_TXDQCTL_NODMACMP);
|
|
|
|
/* Enable autopadding of short TX frames. */
|
|
SF_SETBIT(sc, SF_MACCFG_1, SF_MACCFG1_AUTOPAD);
|
|
|
|
/* Enable interrupts. */
|
|
csr_write_4(sc, SF_IMR, SF_INTRS);
|
|
SF_SETBIT(sc, SF_PCI_DEVCFG, SF_PCIDEVCFG_INTR_ENB);
|
|
|
|
/* Enable the RX and TX engines. */
|
|
SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_RX_ENB|SF_ETHCTL_RXDMA_ENB);
|
|
SF_SETBIT(sc, SF_GEN_ETH_CTL, SF_ETHCTL_TX_ENB|SF_ETHCTL_TXDMA_ENB);
|
|
|
|
/*mii_mediachg(mii);*/
|
|
sf_ifmedia_upd(ifp);
|
|
|
|
ifp->if_flags |= IFF_RUNNING;
|
|
ifp->if_flags &= ~IFF_OACTIVE;
|
|
|
|
sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
|
|
|
|
SF_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
static int
|
|
sf_encap(sc, c, m_head)
|
|
struct sf_softc *sc;
|
|
struct sf_tx_bufdesc_type0 *c;
|
|
struct mbuf *m_head;
|
|
{
|
|
int frag = 0;
|
|
struct sf_frag *f = NULL;
|
|
struct mbuf *m;
|
|
|
|
m = m_head;
|
|
|
|
for (m = m_head, frag = 0; m != NULL; m = m->m_next) {
|
|
if (m->m_len != 0) {
|
|
if (frag == SF_MAXFRAGS)
|
|
break;
|
|
f = &c->sf_frags[frag];
|
|
if (frag == 0)
|
|
f->sf_pktlen = m_head->m_pkthdr.len;
|
|
f->sf_fraglen = m->m_len;
|
|
f->sf_addr = vtophys(mtod(m, vm_offset_t));
|
|
frag++;
|
|
}
|
|
}
|
|
|
|
if (m != NULL) {
|
|
struct mbuf *m_new = NULL;
|
|
|
|
MGETHDR(m_new, M_DONTWAIT, MT_DATA);
|
|
if (m_new == NULL) {
|
|
printf("sf%d: no memory for tx list\n", sc->sf_unit);
|
|
return(1);
|
|
}
|
|
|
|
if (m_head->m_pkthdr.len > MHLEN) {
|
|
MCLGET(m_new, M_DONTWAIT);
|
|
if (!(m_new->m_flags & M_EXT)) {
|
|
m_freem(m_new);
|
|
printf("sf%d: no memory for tx list\n",
|
|
sc->sf_unit);
|
|
return(1);
|
|
}
|
|
}
|
|
m_copydata(m_head, 0, m_head->m_pkthdr.len,
|
|
mtod(m_new, caddr_t));
|
|
m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
|
|
m_freem(m_head);
|
|
m_head = m_new;
|
|
f = &c->sf_frags[0];
|
|
f->sf_fraglen = f->sf_pktlen = m_head->m_pkthdr.len;
|
|
f->sf_addr = vtophys(mtod(m_head, caddr_t));
|
|
frag = 1;
|
|
}
|
|
|
|
c->sf_mbuf = m_head;
|
|
c->sf_id = SF_TX_BUFDESC_ID;
|
|
c->sf_fragcnt = frag;
|
|
c->sf_intr = 1;
|
|
c->sf_caltcp = 0;
|
|
c->sf_crcen = 1;
|
|
|
|
return(0);
|
|
}
|
|
|
|
static void
|
|
sf_start(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct sf_softc *sc;
|
|
struct sf_tx_bufdesc_type0 *cur_tx = NULL;
|
|
struct mbuf *m_head = NULL;
|
|
int i, txprod;
|
|
|
|
sc = ifp->if_softc;
|
|
SF_LOCK(sc);
|
|
|
|
if (!sc->sf_link && ifp->if_snd.ifq_len < 10) {
|
|
SF_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
if (ifp->if_flags & IFF_OACTIVE) {
|
|
SF_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
|
|
i = SF_IDX_HI(txprod) >> 4;
|
|
|
|
if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
|
|
printf("sf%d: TX ring full, resetting\n", sc->sf_unit);
|
|
sf_init(sc);
|
|
txprod = csr_read_4(sc, SF_TXDQ_PRODIDX);
|
|
i = SF_IDX_HI(txprod) >> 4;
|
|
}
|
|
|
|
while(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf == NULL) {
|
|
if (sc->sf_tx_cnt >= (SF_TX_DLIST_CNT - 5)) {
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
cur_tx = NULL;
|
|
break;
|
|
}
|
|
IF_DEQUEUE(&ifp->if_snd, m_head);
|
|
if (m_head == NULL)
|
|
break;
|
|
|
|
cur_tx = &sc->sf_ldata->sf_tx_dlist[i];
|
|
if (sf_encap(sc, cur_tx, m_head)) {
|
|
IF_PREPEND(&ifp->if_snd, m_head);
|
|
ifp->if_flags |= IFF_OACTIVE;
|
|
cur_tx = NULL;
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* If there's a BPF listener, bounce a copy of this frame
|
|
* to him.
|
|
*/
|
|
if (ifp->if_bpf)
|
|
bpf_mtap(ifp, m_head);
|
|
|
|
SF_INC(i, SF_TX_DLIST_CNT);
|
|
sc->sf_tx_cnt++;
|
|
/*
|
|
* Don't get the TX DMA queue get too full.
|
|
*/
|
|
if (sc->sf_tx_cnt > 64)
|
|
break;
|
|
}
|
|
|
|
if (cur_tx == NULL) {
|
|
SF_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
/* Transmit */
|
|
csr_write_4(sc, SF_TXDQ_PRODIDX,
|
|
(txprod & ~SF_TXDQ_PRODIDX_HIPRIO) |
|
|
((i << 20) & 0xFFFF0000));
|
|
|
|
ifp->if_timer = 5;
|
|
|
|
SF_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
sf_stop(sc)
|
|
struct sf_softc *sc;
|
|
{
|
|
int i;
|
|
struct ifnet *ifp;
|
|
|
|
SF_LOCK(sc);
|
|
|
|
ifp = &sc->arpcom.ac_if;
|
|
|
|
untimeout(sf_stats_update, sc, sc->sf_stat_ch);
|
|
|
|
csr_write_4(sc, SF_GEN_ETH_CTL, 0);
|
|
csr_write_4(sc, SF_CQ_CONSIDX, 0);
|
|
csr_write_4(sc, SF_CQ_PRODIDX, 0);
|
|
csr_write_4(sc, SF_RXDQ_ADDR_Q1, 0);
|
|
csr_write_4(sc, SF_RXDQ_CTL_1, 0);
|
|
csr_write_4(sc, SF_RXDQ_PTR_Q1, 0);
|
|
csr_write_4(sc, SF_TXCQ_CTL, 0);
|
|
csr_write_4(sc, SF_TXDQ_ADDR_HIPRIO, 0);
|
|
csr_write_4(sc, SF_TXDQ_CTL, 0);
|
|
sf_reset(sc);
|
|
|
|
sc->sf_link = 0;
|
|
|
|
for (i = 0; i < SF_RX_DLIST_CNT; i++) {
|
|
if (sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf != NULL) {
|
|
m_freem(sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf);
|
|
sc->sf_ldata->sf_rx_dlist_big[i].sf_mbuf = NULL;
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < SF_TX_DLIST_CNT; i++) {
|
|
if (sc->sf_ldata->sf_tx_dlist[i].sf_mbuf != NULL) {
|
|
m_freem(sc->sf_ldata->sf_tx_dlist[i].sf_mbuf);
|
|
sc->sf_ldata->sf_tx_dlist[i].sf_mbuf = NULL;
|
|
}
|
|
}
|
|
|
|
ifp->if_flags &= ~(IFF_RUNNING|IFF_OACTIVE);
|
|
SF_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
/*
|
|
* Note: it is important that this function not be interrupted. We
|
|
* use a two-stage register access scheme: if we are interrupted in
|
|
* between setting the indirect address register and reading from the
|
|
* indirect data register, the contents of the address register could
|
|
* be changed out from under us.
|
|
*/
|
|
static void
|
|
sf_stats_update(xsc)
|
|
void *xsc;
|
|
{
|
|
struct sf_softc *sc;
|
|
struct ifnet *ifp;
|
|
struct mii_data *mii;
|
|
struct sf_stats stats;
|
|
u_int32_t *ptr;
|
|
int i;
|
|
|
|
sc = xsc;
|
|
SF_LOCK(sc);
|
|
ifp = &sc->arpcom.ac_if;
|
|
mii = device_get_softc(sc->sf_miibus);
|
|
|
|
ptr = (u_int32_t *)&stats;
|
|
for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
|
|
ptr[i] = csr_read_4(sc, SF_STATS_BASE +
|
|
(i + sizeof(u_int32_t)));
|
|
|
|
for (i = 0; i < sizeof(stats)/sizeof(u_int32_t); i++)
|
|
csr_write_4(sc, SF_STATS_BASE +
|
|
(i + sizeof(u_int32_t)), 0);
|
|
|
|
ifp->if_collisions += stats.sf_tx_single_colls +
|
|
stats.sf_tx_multi_colls + stats.sf_tx_excess_colls;
|
|
|
|
mii_tick(mii);
|
|
|
|
if (!sc->sf_link && mii->mii_media_status & IFM_ACTIVE &&
|
|
IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
|
|
sc->sf_link++;
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
sf_start(ifp);
|
|
}
|
|
|
|
sc->sf_stat_ch = timeout(sf_stats_update, sc, hz);
|
|
|
|
SF_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
sf_watchdog(ifp)
|
|
struct ifnet *ifp;
|
|
{
|
|
struct sf_softc *sc;
|
|
|
|
sc = ifp->if_softc;
|
|
|
|
SF_LOCK(sc);
|
|
|
|
ifp->if_oerrors++;
|
|
printf("sf%d: watchdog timeout\n", sc->sf_unit);
|
|
|
|
sf_stop(sc);
|
|
sf_reset(sc);
|
|
sf_init(sc);
|
|
|
|
if (ifp->if_snd.ifq_head != NULL)
|
|
sf_start(ifp);
|
|
|
|
SF_UNLOCK(sc);
|
|
|
|
return;
|
|
}
|
|
|
|
static void
|
|
sf_shutdown(dev)
|
|
device_t dev;
|
|
{
|
|
struct sf_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
sf_stop(sc);
|
|
|
|
return;
|
|
}
|