a0a74f77de
The POWER9 MMU (PowerISA 3.0) is slightly different from current configurations, using a partition table even for hypervisor mode, and dropping the SDR1 register. Key off the newly early-enabled CPU features flags for the new architecture, and configure the MMU appropriately. The POWER9 MMU ignores the "PSIZ" field in the PTCR, and expects a 64kB table. As we are enabled for powernv (hypervisor mode, no VMs), only initialize partition table entry 0, and zero out the rest. The actual contents of the register are identical to SDR1 from previous architectures. Along with this, fix a bug in the page table allocation with very large memory. The table can be allocated on any 256k boundary. The bootstrap_alloc alignment argument is an int, and with large amounts of memory passing the size of the table as the alignment will overflow an integer. Hard-code the alignment at 256k as wider alignment is not necessary. Reviewed by: nwhitehorn Tested by: Breno Leitao Relnotes: Yes
90 lines
2.7 KiB
C
90 lines
2.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (C) 2010 Nathan Whitehorn
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _POWERPC_AIM_MMU_OEA64_H
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#define _POWERPC_AIM_MMU_OEA64_H
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#include <machine/mmuvar.h>
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extern mmu_def_t oea64_mmu;
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/*
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* Helper routines
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*/
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/* Allocate physical memory for use in moea64_bootstrap. */
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vm_offset_t moea64_bootstrap_alloc(vm_size_t, u_int);
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/* Set an LPTE structure to match the contents of a PVO */
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void moea64_pte_from_pvo(const struct pvo_entry *pvo, struct lpte *lpte);
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/*
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* Flags
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*/
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#define MOEA64_PTE_PROT_UPDATE 1
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#define MOEA64_PTE_INVALIDATE 2
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/*
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* Bootstrap subroutines
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*
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* An MMU_BOOTSTRAP() implementation looks like this:
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* moea64_early_bootstrap();
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* Allocate Page Table
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* moea64_mid_bootstrap();
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* Add mappings for MMU resources
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* moea64_late_bootstrap();
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*/
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void moea64_early_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
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vm_offset_t kernelend);
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void moea64_mid_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
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vm_offset_t kernelend);
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void moea64_late_bootstrap(mmu_t mmup, vm_offset_t kernelstart,
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vm_offset_t kernelend);
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/*
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* Statistics
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*/
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extern u_int moea64_pte_valid;
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extern u_int moea64_pte_overflow;
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/*
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* State variables
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*/
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extern int moea64_large_page_shift;
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extern uint64_t moea64_large_page_size;
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extern u_long moea64_pteg_count;
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extern u_long moea64_pteg_mask;
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extern int n_slbs;
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#endif /* _POWERPC_AIM_MMU_OEA64_H */
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