f8feb430b0
established, OS shall flush the caches on all processors that may have used the mapping previously. This operation is not needed if processors support self-snooping. If not, but clflush instruction is implemented on the CPU, series of the clflush can be used on the mapping region. Otherwise, we have to flush the whole cache. The later operation is very expensive, and AMD-made CPUs do not have self-snooping. Implement cache flush for remapped region by using clflush for amd64, when supported by CPU. Proposed and reviewed by: alc Approved by: re (kensmith)
736 lines
14 KiB
C
736 lines
14 KiB
C
/*-
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* Copyright (c) 2003 Peter Wemm.
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* Copyright (c) 1993 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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|
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/*
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* Functions to provide access to special i386 instructions.
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* This in included in sys/systm.h, and that file should be
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* used in preference to this.
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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|
|
|
#ifndef _SYS_CDEFS_H_
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#error this file needs sys/cdefs.h as a prerequisite
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#endif
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|
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struct region_descriptor;
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|
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|
#define readb(va) (*(volatile u_int8_t *) (va))
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#define readw(va) (*(volatile u_int16_t *) (va))
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#define readl(va) (*(volatile u_int32_t *) (va))
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#define readq(va) (*(volatile u_int64_t *) (va))
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|
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#define writeb(va, d) (*(volatile u_int8_t *) (va) = (d))
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#define writew(va, d) (*(volatile u_int16_t *) (va) = (d))
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#define writel(va, d) (*(volatile u_int32_t *) (va) = (d))
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#define writeq(va, d) (*(volatile u_int64_t *) (va) = (d))
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|
|
|
#if defined(__GNUCLIKE_ASM) && defined(__CC_SUPPORTS___INLINE)
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|
|
|
static __inline void
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|
breakpoint(void)
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{
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__asm __volatile("int $3");
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}
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|
static __inline u_int
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bsfl(u_int mask)
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{
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u_int result;
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__asm __volatile("bsfl %1,%0" : "=r" (result) : "rm" (mask));
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return (result);
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}
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static __inline u_long
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bsfq(u_long mask)
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{
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u_long result;
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__asm __volatile("bsfq %1,%0" : "=r" (result) : "rm" (mask));
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return (result);
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}
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static __inline u_int
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bsrl(u_int mask)
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{
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u_int result;
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__asm __volatile("bsrl %1,%0" : "=r" (result) : "rm" (mask));
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return (result);
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}
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static __inline u_long
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bsrq(u_long mask)
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|
{
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u_long result;
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|
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__asm __volatile("bsrq %1,%0" : "=r" (result) : "rm" (mask));
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return (result);
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}
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|
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|
static __inline void
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|
clflush(u_long addr)
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|
{
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|
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|
__asm __volatile("clflush %0" : : "m" (*(char *)addr));
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}
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|
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|
static __inline void
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|
disable_intr(void)
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|
{
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|
__asm __volatile("cli" : : : "memory");
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|
}
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|
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|
static __inline void
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|
do_cpuid(u_int ax, u_int *p)
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|
{
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__asm __volatile("cpuid"
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: "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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: "0" (ax));
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|
}
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|
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|
static __inline void
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|
cpuid_count(u_int ax, u_int cx, u_int *p)
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|
{
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__asm __volatile("cpuid"
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: "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3])
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: "0" (ax), "c" (cx));
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|
}
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|
|
|
static __inline void
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|
enable_intr(void)
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|
{
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__asm __volatile("sti");
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|
}
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|
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|
#ifdef _KERNEL
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|
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|
#define HAVE_INLINE_FFS
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|
#define ffs(x) __builtin_ffs(x)
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|
|
|
#define HAVE_INLINE_FFSL
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|
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|
static __inline int
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|
ffsl(long mask)
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|
{
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|
return (mask == 0 ? mask : (int)bsfq((u_long)mask) + 1);
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}
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|
|
|
#define HAVE_INLINE_FLS
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|
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|
static __inline int
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|
fls(int mask)
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|
{
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return (mask == 0 ? mask : (int)bsrl((u_int)mask) + 1);
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|
}
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|
|
|
#define HAVE_INLINE_FLSL
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|
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|
static __inline int
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|
flsl(long mask)
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|
{
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|
return (mask == 0 ? mask : (int)bsrq((u_long)mask) + 1);
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}
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|
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|
#endif /* _KERNEL */
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|
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|
static __inline void
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|
halt(void)
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|
{
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|
__asm __volatile("hlt");
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|
}
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|
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|
static __inline u_char
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|
inb(u_int port)
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|
{
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|
u_char data;
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|
__asm volatile("inb %w1, %0" : "=a" (data) : "Nd" (port));
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return (data);
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}
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|
static __inline u_int
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|
inl(u_int port)
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|
{
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|
u_int data;
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|
__asm volatile("inl %w1, %0" : "=a" (data) : "Nd" (port));
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return (data);
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}
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static __inline void
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insb(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insb"
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: "+D" (addr), "+c" (cnt)
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: "d" (port)
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: "memory");
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}
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|
static __inline void
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|
insw(u_int port, void *addr, size_t cnt)
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{
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__asm __volatile("cld; rep; insw"
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: "+D" (addr), "+c" (cnt)
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: "d" (port)
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: "memory");
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|
}
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|
static __inline void
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|
insl(u_int port, void *addr, size_t cnt)
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|
{
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__asm __volatile("cld; rep; insl"
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: "+D" (addr), "+c" (cnt)
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: "d" (port)
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: "memory");
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|
}
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|
|
|
static __inline void
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|
invd(void)
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|
{
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|
__asm __volatile("invd");
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|
}
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|
static __inline u_short
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|
inw(u_int port)
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|
{
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|
u_short data;
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|
__asm volatile("inw %w1, %0" : "=a" (data) : "Nd" (port));
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return (data);
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|
}
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|
static __inline void
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|
outb(u_int port, u_char data)
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|
{
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|
__asm volatile("outb %0, %w1" : : "a" (data), "Nd" (port));
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|
}
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|
static __inline void
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outl(u_int port, u_int data)
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|
{
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|
__asm volatile("outl %0, %w1" : : "a" (data), "Nd" (port));
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|
}
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|
static __inline void
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|
outsb(u_int port, const void *addr, size_t cnt)
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|
{
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|
__asm __volatile("cld; rep; outsb"
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: "+S" (addr), "+c" (cnt)
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: "d" (port));
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|
}
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|
static __inline void
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|
outsw(u_int port, const void *addr, size_t cnt)
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|
{
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|
__asm __volatile("cld; rep; outsw"
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: "+S" (addr), "+c" (cnt)
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: "d" (port));
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|
}
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|
static __inline void
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|
outsl(u_int port, const void *addr, size_t cnt)
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|
{
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|
__asm __volatile("cld; rep; outsl"
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: "+S" (addr), "+c" (cnt)
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: "d" (port));
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|
}
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|
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|
static __inline void
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|
outw(u_int port, u_short data)
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|
{
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|
__asm volatile("outw %0, %w1" : : "a" (data), "Nd" (port));
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|
}
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|
static __inline void
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|
mfence(void)
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|
{
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|
__asm__ __volatile("mfence" : : : "memory");
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|
}
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|
|
|
static __inline void
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|
ia32_pause(void)
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|
{
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|
__asm __volatile("pause");
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|
}
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|
|
|
static __inline u_long
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|
read_rflags(void)
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|
{
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|
u_long rf;
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|
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|
__asm __volatile("pushfq; popq %0" : "=r" (rf));
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|
return (rf);
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|
}
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|
|
|
static __inline u_int64_t
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|
rdmsr(u_int msr)
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|
{
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|
u_int32_t low, high;
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|
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|
__asm __volatile("rdmsr" : "=a" (low), "=d" (high) : "c" (msr));
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return (low | ((u_int64_t)high << 32));
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}
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|
|
|
static __inline u_int64_t
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|
rdpmc(u_int pmc)
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|
{
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|
u_int32_t low, high;
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|
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|
__asm __volatile("rdpmc" : "=a" (low), "=d" (high) : "c" (pmc));
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return (low | ((u_int64_t)high << 32));
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}
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|
|
|
static __inline u_int64_t
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|
rdtsc(void)
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|
{
|
|
u_int32_t low, high;
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|
|
|
__asm __volatile("rdtsc" : "=a" (low), "=d" (high));
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return (low | ((u_int64_t)high << 32));
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}
|
|
|
|
static __inline void
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|
wbinvd(void)
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|
{
|
|
__asm __volatile("wbinvd");
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|
}
|
|
|
|
static __inline void
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|
write_rflags(u_long rf)
|
|
{
|
|
__asm __volatile("pushq %0; popfq" : : "r" (rf));
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|
}
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|
|
|
static __inline void
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|
wrmsr(u_int msr, u_int64_t newval)
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|
{
|
|
u_int32_t low, high;
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|
|
|
low = newval;
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high = newval >> 32;
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|
__asm __volatile("wrmsr" : : "a" (low), "d" (high), "c" (msr));
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|
}
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|
|
|
static __inline void
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|
load_cr0(u_long data)
|
|
{
|
|
|
|
__asm __volatile("movq %0,%%cr0" : : "r" (data));
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|
}
|
|
|
|
static __inline u_long
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|
rcr0(void)
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|
{
|
|
u_long data;
|
|
|
|
__asm __volatile("movq %%cr0,%0" : "=r" (data));
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|
return (data);
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|
}
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|
|
|
static __inline u_long
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|
rcr2(void)
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|
{
|
|
u_long data;
|
|
|
|
__asm __volatile("movq %%cr2,%0" : "=r" (data));
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|
return (data);
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|
}
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|
|
|
static __inline void
|
|
load_cr3(u_long data)
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|
{
|
|
|
|
__asm __volatile("movq %0,%%cr3" : : "r" (data) : "memory");
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|
}
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|
|
|
static __inline u_long
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|
rcr3(void)
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|
{
|
|
u_long data;
|
|
|
|
__asm __volatile("movq %%cr3,%0" : "=r" (data));
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|
return (data);
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|
}
|
|
|
|
static __inline void
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|
load_cr4(u_long data)
|
|
{
|
|
__asm __volatile("movq %0,%%cr4" : : "r" (data));
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|
}
|
|
|
|
static __inline u_long
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|
rcr4(void)
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|
{
|
|
u_long data;
|
|
|
|
__asm __volatile("movq %%cr4,%0" : "=r" (data));
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|
return (data);
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|
}
|
|
|
|
/*
|
|
* Global TLB flush (except for thise for pages marked PG_G)
|
|
*/
|
|
static __inline void
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|
invltlb(void)
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|
{
|
|
|
|
load_cr3(rcr3());
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|
}
|
|
|
|
/*
|
|
* TLB flush for an individual page (even if it has PG_G).
|
|
* Only works on 486+ CPUs (i386 does not have PG_G).
|
|
*/
|
|
static __inline void
|
|
invlpg(u_long addr)
|
|
{
|
|
|
|
__asm __volatile("invlpg %0" : : "m" (*(char *)addr) : "memory");
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|
}
|
|
|
|
static __inline u_int
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|
rfs(void)
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|
{
|
|
u_int sel;
|
|
__asm __volatile("mov %%fs,%0" : "=rm" (sel));
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|
return (sel);
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|
}
|
|
|
|
static __inline u_int
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|
rgs(void)
|
|
{
|
|
u_int sel;
|
|
__asm __volatile("mov %%gs,%0" : "=rm" (sel));
|
|
return (sel);
|
|
}
|
|
|
|
static __inline u_int
|
|
rss(void)
|
|
{
|
|
u_int sel;
|
|
__asm __volatile("mov %%ss,%0" : "=rm" (sel));
|
|
return (sel);
|
|
}
|
|
|
|
static __inline void
|
|
load_ds(u_int sel)
|
|
{
|
|
__asm __volatile("mov %0,%%ds" : : "rm" (sel));
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|
}
|
|
|
|
static __inline void
|
|
load_es(u_int sel)
|
|
{
|
|
__asm __volatile("mov %0,%%es" : : "rm" (sel));
|
|
}
|
|
|
|
static inline void
|
|
cpu_monitor(const void *addr, int extensions, int hints)
|
|
{
|
|
__asm __volatile("monitor;"
|
|
: :"a" (addr), "c" (extensions), "d"(hints));
|
|
}
|
|
|
|
static inline void
|
|
cpu_mwait(int extensions, int hints)
|
|
{
|
|
__asm __volatile("mwait;" : :"a" (hints), "c" (extensions));
|
|
}
|
|
|
|
#ifdef _KERNEL
|
|
/* This is defined in <machine/specialreg.h> but is too painful to get to */
|
|
#ifndef MSR_FSBASE
|
|
#define MSR_FSBASE 0xc0000100
|
|
#endif
|
|
static __inline void
|
|
load_fs(u_int sel)
|
|
{
|
|
/* Preserve the fsbase value across the selector load */
|
|
__asm __volatile("rdmsr; mov %0,%%fs; wrmsr"
|
|
: : "rm" (sel), "c" (MSR_FSBASE) : "eax", "edx");
|
|
}
|
|
|
|
#ifndef MSR_GSBASE
|
|
#define MSR_GSBASE 0xc0000101
|
|
#endif
|
|
static __inline void
|
|
load_gs(u_int sel)
|
|
{
|
|
/*
|
|
* Preserve the gsbase value across the selector load.
|
|
* Note that we have to disable interrupts because the gsbase
|
|
* being trashed happens to be the kernel gsbase at the time.
|
|
*/
|
|
__asm __volatile("pushfq; cli; rdmsr; mov %0,%%gs; wrmsr; popfq"
|
|
: : "rm" (sel), "c" (MSR_GSBASE) : "eax", "edx");
|
|
}
|
|
#else
|
|
/* Usable by userland */
|
|
static __inline void
|
|
load_fs(u_int sel)
|
|
{
|
|
__asm __volatile("mov %0,%%fs" : : "rm" (sel));
|
|
}
|
|
|
|
static __inline void
|
|
load_gs(u_int sel)
|
|
{
|
|
__asm __volatile("mov %0,%%gs" : : "rm" (sel));
|
|
}
|
|
#endif
|
|
|
|
static __inline void
|
|
lidt(struct region_descriptor *addr)
|
|
{
|
|
__asm __volatile("lidt (%0)" : : "r" (addr));
|
|
}
|
|
|
|
static __inline void
|
|
lldt(u_short sel)
|
|
{
|
|
__asm __volatile("lldt %0" : : "r" (sel));
|
|
}
|
|
|
|
static __inline void
|
|
ltr(u_short sel)
|
|
{
|
|
__asm __volatile("ltr %0" : : "r" (sel));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr0(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr0,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr0(u_int64_t dr0)
|
|
{
|
|
__asm __volatile("movq %0,%%dr0" : : "r" (dr0));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr1(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr1,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr1(u_int64_t dr1)
|
|
{
|
|
__asm __volatile("movq %0,%%dr1" : : "r" (dr1));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr2(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr2,%0" : "=r" (data));
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|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr2(u_int64_t dr2)
|
|
{
|
|
__asm __volatile("movq %0,%%dr2" : : "r" (dr2));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr3(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr3,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr3(u_int64_t dr3)
|
|
{
|
|
__asm __volatile("movq %0,%%dr3" : : "r" (dr3));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr4(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr4,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr4(u_int64_t dr4)
|
|
{
|
|
__asm __volatile("movq %0,%%dr4" : : "r" (dr4));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr5(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr5,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr5(u_int64_t dr5)
|
|
{
|
|
__asm __volatile("movq %0,%%dr5" : : "r" (dr5));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr6(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr6,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr6(u_int64_t dr6)
|
|
{
|
|
__asm __volatile("movq %0,%%dr6" : : "r" (dr6));
|
|
}
|
|
|
|
static __inline u_int64_t
|
|
rdr7(void)
|
|
{
|
|
u_int64_t data;
|
|
__asm __volatile("movq %%dr7,%0" : "=r" (data));
|
|
return (data);
|
|
}
|
|
|
|
static __inline void
|
|
load_dr7(u_int64_t dr7)
|
|
{
|
|
__asm __volatile("movq %0,%%dr7" : : "r" (dr7));
|
|
}
|
|
|
|
static __inline register_t
|
|
intr_disable(void)
|
|
{
|
|
register_t rflags;
|
|
|
|
rflags = read_rflags();
|
|
disable_intr();
|
|
return (rflags);
|
|
}
|
|
|
|
static __inline void
|
|
intr_restore(register_t rflags)
|
|
{
|
|
write_rflags(rflags);
|
|
}
|
|
|
|
#else /* !(__GNUCLIKE_ASM && __CC_SUPPORTS___INLINE) */
|
|
|
|
int breakpoint(void);
|
|
u_int bsfl(u_int mask);
|
|
u_int bsrl(u_int mask);
|
|
void disable_intr(void);
|
|
void do_cpuid(u_int ax, u_int *p);
|
|
void enable_intr(void);
|
|
void halt(void);
|
|
void ia32_pause(void);
|
|
u_char inb(u_int port);
|
|
u_int inl(u_int port);
|
|
void insb(u_int port, void *addr, size_t cnt);
|
|
void insl(u_int port, void *addr, size_t cnt);
|
|
void insw(u_int port, void *addr, size_t cnt);
|
|
register_t intr_disable(void);
|
|
void intr_restore(register_t rf);
|
|
void invd(void);
|
|
void invlpg(u_int addr);
|
|
void invltlb(void);
|
|
u_short inw(u_int port);
|
|
void lidt(struct region_descriptor *addr);
|
|
void lldt(u_short sel);
|
|
void load_cr0(u_long cr0);
|
|
void load_cr3(u_long cr3);
|
|
void load_cr4(u_long cr4);
|
|
void load_dr0(u_int64_t dr0);
|
|
void load_dr1(u_int64_t dr1);
|
|
void load_dr2(u_int64_t dr2);
|
|
void load_dr3(u_int64_t dr3);
|
|
void load_dr4(u_int64_t dr4);
|
|
void load_dr5(u_int64_t dr5);
|
|
void load_dr6(u_int64_t dr6);
|
|
void load_dr7(u_int64_t dr7);
|
|
void load_fs(u_int sel);
|
|
void load_gs(u_int sel);
|
|
void ltr(u_short sel);
|
|
void outb(u_int port, u_char data);
|
|
void outl(u_int port, u_int data);
|
|
void outsb(u_int port, const void *addr, size_t cnt);
|
|
void outsl(u_int port, const void *addr, size_t cnt);
|
|
void outsw(u_int port, const void *addr, size_t cnt);
|
|
void outw(u_int port, u_short data);
|
|
u_long rcr0(void);
|
|
u_long rcr2(void);
|
|
u_long rcr3(void);
|
|
u_long rcr4(void);
|
|
u_int64_t rdmsr(u_int msr);
|
|
u_int64_t rdpmc(u_int pmc);
|
|
u_int64_t rdr0(void);
|
|
u_int64_t rdr1(void);
|
|
u_int64_t rdr2(void);
|
|
u_int64_t rdr3(void);
|
|
u_int64_t rdr4(void);
|
|
u_int64_t rdr5(void);
|
|
u_int64_t rdr6(void);
|
|
u_int64_t rdr7(void);
|
|
u_int64_t rdtsc(void);
|
|
u_int read_rflags(void);
|
|
u_int rfs(void);
|
|
u_int rgs(void);
|
|
void wbinvd(void);
|
|
void write_rflags(u_int rf);
|
|
void wrmsr(u_int msr, u_int64_t newval);
|
|
|
|
#endif /* __GNUCLIKE_ASM && __CC_SUPPORTS___INLINE */
|
|
|
|
void reset_dbregs(void);
|
|
|
|
#ifdef _KERNEL
|
|
int rdmsr_safe(u_int msr, uint64_t *val);
|
|
int wrmsr_safe(u_int msr, uint64_t newval);
|
|
#endif
|
|
|
|
#endif /* !_MACHINE_CPUFUNC_H_ */
|