78cc33fd32
L3 cache is not defined by Book-E, so is platform specific. Since it was already moved for e500-based devices into mpc85xx in r292903, just eliminate it altogether. Any device that supports L3 cache should have its own platform means to enable it.
215 lines
5.9 KiB
C
215 lines
5.9 KiB
C
/*-
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* Copyright (c) 2011-2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/systm.h>
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#include <machine/machdep.h>
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#include <powerpc/booke/dcr.h>
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#include <powerpc/apm86xxx/apm86xxx.h>
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#include <dev/fdt/fdt_common.h>
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#define OCP_ADDR_WORDLO(addr) ((uint32_t)((uint64_t)(addr) & 0xFFFFFFFF))
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#define OCP_ADDR_WORDHI(addr) ((uint32_t)((uint64_t)(addr) >> 32))
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extern void tlb_write(u_int, uint32_t, uint32_t, uint32_t, tlbtid_t, uint32_t,
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uint32_t);
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extern void tlb_read(u_int, uint32_t *, uint32_t *, uint32_t *, uint32_t *,
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uint32_t *, uint32_t *);
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unsigned int tlb_static_entries;
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unsigned int tlb_current_entry = TLB_SIZE;
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unsigned int tlb_misses = 0;
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unsigned int tlb_invals = 0;
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void tlb_map(uint32_t, uint32_t, uint32_t, uint32_t, uint32_t);
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void tlb_map_mem(uint32_t, uint32_t, uint32_t);
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void tlb_dump(void);
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void
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booke_init_tlb(vm_paddr_t fdt_immr_pa)
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{
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/* Map register space */
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tlb_map(APM86XXX_DEEP_SLEEP_VA,
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OCP_ADDR_WORDLO(APM86XXX_DEEP_SLEEP_PA),
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OCP_ADDR_WORDHI(APM86XXX_DEEP_SLEEP_PA), TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_CSR_VA, OCP_ADDR_WORDLO(APM86XXX_CSR_PA),
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OCP_ADDR_WORDHI(APM86XXX_CSR_PA), TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_PRIMARY_FABRIC_VA,
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OCP_ADDR_WORDLO(APM86XXX_PRIMARY_FABRIC_PA),
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OCP_ADDR_WORDHI(APM86XXX_PRIMARY_FABRIC_PA),
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TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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tlb_map(APM86XXX_AHB_VA, OCP_ADDR_WORDLO(APM86XXX_AHB_PA),
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OCP_ADDR_WORDHI(APM86XXX_AHB_PA),
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TLB_VALID | TLB_SIZE_16M,
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TLB_SW | TLB_SR | TLB_I | TLB_G);
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/* Map MailBox space */
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tlb_map(APM86XXX_MBOX_VA, OCP_ADDR_WORDLO(APM86XXX_MBOX_PA),
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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tlb_map(APM86XXX_MBOX_VA + 0x1000,
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OCP_ADDR_WORDLO(APM86XXX_MBOX_PA) + 0x1000,
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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tlb_map(APM86XXX_MBOX_VA + 0x2000,
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OCP_ADDR_WORDLO(APM86XXX_MBOX_PA)+ 0x2000,
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OCP_ADDR_WORDHI(APM86XXX_MBOX_PA),
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TLB_VALID | TLB_SIZE_4K,
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TLB_UX | TLB_UW | TLB_UR |
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TLB_SX | TLB_SW | TLB_SR |
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TLB_I | TLB_G);
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}
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void
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booke_enable_l1_cache(void)
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{
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}
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void
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booke_enable_l2_cache(void)
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{
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}
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void
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booke_disable_l2_cache(void)
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{
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uint32_t ccr1,l2cr0;
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/* Disable L2 cache op broadcast */
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ccr1 = mfspr(SPR_CCR1);
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ccr1 &= ~CCR1_L2COBE;
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mtspr(SPR_CCR1, ccr1);
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/* Set L2 array size to 0 i.e. disable L2 cache */
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mtdcr(DCR_L2DCDCRAI, DCR_L2CR0);
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l2cr0 = mfdcr(DCR_L2DCDCRDI);
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l2cr0 &= ~L2CR0_AS;
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mtdcr(DCR_L2DCDCRDI, l2cr0);
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}
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void tlb_map(uint32_t epn, uint32_t rpn, uint32_t erpn, uint32_t flags,
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uint32_t perms)
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{
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tlb_write(++tlb_static_entries, epn, rpn, erpn, 0, flags, perms);
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}
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static void tlb_dump_entry(u_int entry)
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{
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uint32_t epn, rpn, erpn, tid, flags, perms;
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const char *size;
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tlb_read(entry, &epn, &rpn, &erpn, &tid, &flags, &perms);
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switch (flags & TLB_SIZE_MASK) {
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case TLB_SIZE_1K:
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size = " 1k";
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break;
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case TLB_SIZE_4K:
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size = " 4k";
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break;
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case TLB_SIZE_16K:
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size = " 16k";
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break;
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case TLB_SIZE_256K:
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size = "256k";
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break;
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case TLB_SIZE_1M:
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size = " 1M";
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break;
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case TLB_SIZE_16M:
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size = " 16M";
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break;
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case TLB_SIZE_256M:
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size = "256M";
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break;
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case TLB_SIZE_1G:
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size = " 1G";
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break;
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default:
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size = "????";
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break;
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}
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printf("TLB[%02u]: 0x%08X => "
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"0x%01X_%08X %s %c %c %s %s %s %s %s "
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"%c%c%c%c%c%c%c%c%c%c%c%c%c%c%c (%u)\n",
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entry, epn, erpn, rpn, size,
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(flags & TLB_TS) ? '1' : '0',
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(flags & TLB_VALID) ? 'V' : '.',
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(perms & TLB_WL1) ? "WL1" : "___",
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(perms & TLB_IL1I) ? "IL1I" : "____",
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(perms & TLB_IL1D) ? "IL1D" : "____",
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(perms & TLB_IL2I) ? "IL2I" : "____",
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(perms & TLB_IL2D) ? "IL2D" : "____",
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(perms & TLB_U0) ? '1' : '.',
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(perms & TLB_U1) ? '2' : '.',
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(perms & TLB_U2) ? '3' : '.',
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(perms & TLB_U3) ? '4' : '.',
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(perms & TLB_W) ? 'W' : '.',
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(perms & TLB_I) ? 'I' : '.',
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(perms & TLB_M) ? 'M' : '.',
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(perms & TLB_G) ? 'G' : '.',
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(perms & TLB_E) ? 'E' : '.',
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(perms & TLB_UX) ? 'x' : '.',
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(perms & TLB_UW) ? 'w' : '.',
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(perms & TLB_UR) ? 'r' : '.',
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(perms & TLB_SX) ? 'X' : '.',
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(perms & TLB_SW) ? 'W' : '.',
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(perms & TLB_SR) ? 'R' : '.',
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tid);
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}
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void tlb_dump(void)
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{
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int i;
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for (i = 0; i < TLB_SIZE; i++)
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tlb_dump_entry(i);
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}
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