1429 lines
37 KiB
C
1429 lines
37 KiB
C
/*-
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* Copyright (c) 1990 William Jolitz.
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)npx.c 7.2 (Berkeley) 5/12/91
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include "opt_isa.h"
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#include "opt_npx.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/mutex.h>
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#include <sys/proc.h>
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#include <sys/smp.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#ifdef NPX_DEBUG
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#include <sys/syslog.h>
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#endif
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#include <sys/signalvar.h>
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#include <vm/uma.h>
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#include <machine/asmacros.h>
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#include <machine/cputypes.h>
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#include <machine/frame.h>
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#include <machine/md_var.h>
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#include <machine/pcb.h>
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#include <machine/psl.h>
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#include <machine/resource.h>
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#include <machine/specialreg.h>
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#include <machine/segments.h>
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#include <machine/ucontext.h>
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#include <machine/intr_machdep.h>
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#ifdef DEV_ISA
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#include <isa/isavar.h>
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#endif
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/*
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* 387 and 287 Numeric Coprocessor Extension (NPX) Driver.
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*/
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#if defined(__GNUCLIKE_ASM) && !defined(lint)
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#define fldcw(cw) __asm __volatile("fldcw %0" : : "m" (cw))
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#define fnclex() __asm __volatile("fnclex")
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#define fninit() __asm __volatile("fninit")
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#define fnsave(addr) __asm __volatile("fnsave %0" : "=m" (*(addr)))
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#define fnstcw(addr) __asm __volatile("fnstcw %0" : "=m" (*(addr)))
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#define fnstsw(addr) __asm __volatile("fnstsw %0" : "=am" (*(addr)))
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#define fp_divide_by_0() __asm __volatile( \
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"fldz; fld1; fdiv %st,%st(1); fnop")
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#define frstor(addr) __asm __volatile("frstor %0" : : "m" (*(addr)))
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#define fxrstor(addr) __asm __volatile("fxrstor %0" : : "m" (*(addr)))
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#define fxsave(addr) __asm __volatile("fxsave %0" : "=m" (*(addr)))
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#define ldmxcsr(csr) __asm __volatile("ldmxcsr %0" : : "m" (csr))
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#define stmxcsr(addr) __asm __volatile("stmxcsr %0" : : "m" (*(addr)))
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static __inline void
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xrstor(char *addr, uint64_t mask)
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{
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uint32_t low, hi;
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low = mask;
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hi = mask >> 32;
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__asm __volatile("xrstor %0" : : "m" (*addr), "a" (low), "d" (hi));
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}
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static __inline void
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xsave(char *addr, uint64_t mask)
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{
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uint32_t low, hi;
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low = mask;
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hi = mask >> 32;
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__asm __volatile("xsave %0" : "=m" (*addr) : "a" (low), "d" (hi) :
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"memory");
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}
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static __inline void
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xsaveopt(char *addr, uint64_t mask)
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{
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uint32_t low, hi;
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low = mask;
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hi = mask >> 32;
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__asm __volatile("xsaveopt %0" : "=m" (*addr) : "a" (low), "d" (hi) :
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"memory");
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}
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#else /* !(__GNUCLIKE_ASM && !lint) */
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void fldcw(u_short cw);
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void fnclex(void);
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void fninit(void);
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void fnsave(caddr_t addr);
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void fnstcw(caddr_t addr);
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void fnstsw(caddr_t addr);
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void fp_divide_by_0(void);
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void frstor(caddr_t addr);
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void fxsave(caddr_t addr);
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void fxrstor(caddr_t addr);
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void ldmxcsr(u_int csr);
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void stmxcsr(u_int *csr);
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void xrstor(char *addr, uint64_t mask);
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void xsave(char *addr, uint64_t mask);
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void xsaveopt(char *addr, uint64_t mask);
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#endif /* __GNUCLIKE_ASM && !lint */
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#define start_emulating() load_cr0(rcr0() | CR0_TS)
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#define stop_emulating() clts()
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#define GET_FPU_CW(thread) \
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(cpu_fxsr ? \
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(thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_cw : \
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(thread)->td_pcb->pcb_save->sv_87.sv_env.en_cw)
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#define GET_FPU_SW(thread) \
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(cpu_fxsr ? \
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(thread)->td_pcb->pcb_save->sv_xmm.sv_env.en_sw : \
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(thread)->td_pcb->pcb_save->sv_87.sv_env.en_sw)
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#define SET_FPU_CW(savefpu, value) do { \
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if (cpu_fxsr) \
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(savefpu)->sv_xmm.sv_env.en_cw = (value); \
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else \
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(savefpu)->sv_87.sv_env.en_cw = (value); \
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} while (0)
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CTASSERT(sizeof(union savefpu) == 512);
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CTASSERT(sizeof(struct xstate_hdr) == 64);
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CTASSERT(sizeof(struct savefpu_ymm) == 832);
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/*
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* This requirement is to make it easier for asm code to calculate
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* offset of the fpu save area from the pcb address. FPU save area
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* must be 64-byte aligned.
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*/
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CTASSERT(sizeof(struct pcb) % XSAVE_AREA_ALIGN == 0);
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/*
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* Ensure the copy of XCR0 saved in a core is contained in the padding
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* area.
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*/
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CTASSERT(X86_XSTATE_XCR0_OFFSET >= offsetof(struct savexmm, sv_pad) &&
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X86_XSTATE_XCR0_OFFSET + sizeof(uint64_t) <= sizeof(struct savexmm));
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static void fpu_clean_state(void);
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static void fpusave(union savefpu *);
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static void fpurstor(union savefpu *);
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int hw_float;
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SYSCTL_INT(_hw, HW_FLOATINGPT, floatingpoint, CTLFLAG_RD,
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&hw_float, 0, "Floating point instructions executed in hardware");
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int use_xsave;
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uint64_t xsave_mask;
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static uma_zone_t fpu_save_area_zone;
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static union savefpu *npx_initialstate;
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struct xsave_area_elm_descr {
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u_int offset;
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u_int size;
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} *xsave_area_desc;
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static int use_xsaveopt;
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static volatile u_int npx_traps_while_probing;
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alias_for_inthand_t probetrap;
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__asm(" \n\
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.text \n\
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.p2align 2,0x90 \n\
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.type " __XSTRING(CNAME(probetrap)) ",@function \n\
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" __XSTRING(CNAME(probetrap)) ": \n\
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ss \n\
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incl " __XSTRING(CNAME(npx_traps_while_probing)) " \n\
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fnclex \n\
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iret \n\
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");
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/*
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* Determine if an FPU is present and how to use it.
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*/
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static int
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npx_probe(void)
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{
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struct gate_descriptor save_idt_npxtrap;
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u_short control, status;
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/*
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* Modern CPUs all have an FPU that uses the INT16 interface
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* and provide a simple way to verify that, so handle the
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* common case right away.
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*/
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if (cpu_feature & CPUID_FPU) {
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hw_float = 1;
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return (1);
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}
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save_idt_npxtrap = idt[IDT_MF];
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setidt(IDT_MF, probetrap, SDT_SYS386TGT, SEL_KPL,
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GSEL(GCODE_SEL, SEL_KPL));
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/*
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* Don't trap while we're probing.
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*/
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stop_emulating();
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/*
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* Finish resetting the coprocessor, if any. If there is an error
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* pending, then we may get a bogus IRQ13, but npx_intr() will handle
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* it OK. Bogus halts have never been observed, but we enabled
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* IRQ13 and cleared the BUSY# latch early to handle them anyway.
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*/
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fninit();
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/*
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* Don't use fwait here because it might hang.
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* Don't use fnop here because it usually hangs if there is no FPU.
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*/
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DELAY(1000); /* wait for any IRQ13 */
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#ifdef DIAGNOSTIC
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if (npx_traps_while_probing != 0)
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printf("fninit caused %u bogus npx trap(s)\n",
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npx_traps_while_probing);
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#endif
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/*
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* Check for a status of mostly zero.
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*/
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status = 0x5a5a;
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fnstsw(&status);
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if ((status & 0xb8ff) == 0) {
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/*
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* Good, now check for a proper control word.
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*/
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control = 0x5a5a;
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fnstcw(&control);
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if ((control & 0x1f3f) == 0x033f) {
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/*
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* We have an npx, now divide by 0 to see if exception
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* 16 works.
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*/
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control &= ~(1 << 2); /* enable divide by 0 trap */
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fldcw(control);
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npx_traps_while_probing = 0;
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fp_divide_by_0();
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if (npx_traps_while_probing != 0) {
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/*
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* Good, exception 16 works.
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*/
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hw_float = 1;
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goto cleanup;
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}
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printf(
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"FPU does not use exception 16 for error reporting\n");
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goto cleanup;
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}
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}
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/*
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* Probe failed. Floating point simply won't work.
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* Notify user and disable FPU/MMX/SSE instruction execution.
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*/
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printf("WARNING: no FPU!\n");
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__asm __volatile("smsw %%ax; orb %0,%%al; lmsw %%ax" : :
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"n" (CR0_EM | CR0_MP) : "ax");
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cleanup:
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idt[IDT_MF] = save_idt_npxtrap;
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return (hw_float);
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}
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/*
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* Enable XSAVE if supported and allowed by user.
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* Calculate the xsave_mask.
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*/
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static void
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npxinit_bsp1(void)
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{
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u_int cp[4];
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uint64_t xsave_mask_user;
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if (cpu_fxsr && (cpu_feature2 & CPUID2_XSAVE) != 0) {
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use_xsave = 1;
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TUNABLE_INT_FETCH("hw.use_xsave", &use_xsave);
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}
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if (!use_xsave)
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return;
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cpuid_count(0xd, 0x0, cp);
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xsave_mask = XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
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if ((cp[0] & xsave_mask) != xsave_mask)
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panic("CPU0 does not support X87 or SSE: %x", cp[0]);
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xsave_mask = ((uint64_t)cp[3] << 32) | cp[0];
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xsave_mask_user = xsave_mask;
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TUNABLE_QUAD_FETCH("hw.xsave_mask", &xsave_mask_user);
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xsave_mask_user |= XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE;
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xsave_mask &= xsave_mask_user;
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if ((xsave_mask & XFEATURE_AVX512) != XFEATURE_AVX512)
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xsave_mask &= ~XFEATURE_AVX512;
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if ((xsave_mask & XFEATURE_MPX) != XFEATURE_MPX)
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xsave_mask &= ~XFEATURE_MPX;
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cpuid_count(0xd, 0x1, cp);
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if ((cp[0] & CPUID_EXTSTATE_XSAVEOPT) != 0)
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use_xsaveopt = 1;
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}
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/*
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* Calculate the fpu save area size.
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*/
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static void
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npxinit_bsp2(void)
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{
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u_int cp[4];
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if (use_xsave) {
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cpuid_count(0xd, 0x0, cp);
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cpu_max_ext_state_size = cp[1];
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/*
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* Reload the cpu_feature2, since we enabled OSXSAVE.
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*/
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do_cpuid(1, cp);
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cpu_feature2 = cp[2];
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} else
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cpu_max_ext_state_size = sizeof(union savefpu);
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}
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/*
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* Initialize floating point unit.
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*/
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void
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npxinit(bool bsp)
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{
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static union savefpu dummy;
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register_t saveintr;
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u_int mxcsr;
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u_short control;
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if (bsp) {
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if (!npx_probe())
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return;
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npxinit_bsp1();
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}
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if (use_xsave) {
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load_cr4(rcr4() | CR4_XSAVE);
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load_xcr(XCR0, xsave_mask);
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}
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/*
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* XCR0 shall be set up before CPU can report the save area size.
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*/
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if (bsp)
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npxinit_bsp2();
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/*
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* fninit has the same h/w bugs as fnsave. Use the detoxified
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* fnsave to throw away any junk in the fpu. fpusave() initializes
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* the fpu.
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*
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* It is too early for critical_enter() to work on AP.
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*/
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saveintr = intr_disable();
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stop_emulating();
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if (cpu_fxsr)
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fninit();
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else
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fnsave(&dummy);
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control = __INITIAL_NPXCW__;
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fldcw(control);
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if (cpu_fxsr) {
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mxcsr = __INITIAL_MXCSR__;
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ldmxcsr(mxcsr);
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}
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start_emulating();
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intr_restore(saveintr);
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}
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/*
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* On the boot CPU we generate a clean state that is used to
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* initialize the floating point unit when it is first used by a
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* process.
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*/
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static void
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npxinitstate(void *arg __unused)
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{
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register_t saveintr;
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int cp[4], i, max_ext_n;
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if (!hw_float)
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return;
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npx_initialstate = malloc(cpu_max_ext_state_size, M_DEVBUF,
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M_WAITOK | M_ZERO);
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saveintr = intr_disable();
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stop_emulating();
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fpusave(npx_initialstate);
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if (cpu_fxsr) {
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if (npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask)
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cpu_mxcsr_mask =
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npx_initialstate->sv_xmm.sv_env.en_mxcsr_mask;
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else
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cpu_mxcsr_mask = 0xFFBF;
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/*
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* The fninit instruction does not modify XMM
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* registers or x87 registers (MM/ST). The fpusave
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* call dumped the garbage contained in the registers
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* after reset to the initial state saved. Clear XMM
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* and x87 registers file image to make the startup
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* program state and signal handler XMM/x87 register
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* content predictable.
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*/
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bzero(npx_initialstate->sv_xmm.sv_fp,
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sizeof(npx_initialstate->sv_xmm.sv_fp));
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bzero(npx_initialstate->sv_xmm.sv_xmm,
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sizeof(npx_initialstate->sv_xmm.sv_xmm));
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} else
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bzero(npx_initialstate->sv_87.sv_ac,
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sizeof(npx_initialstate->sv_87.sv_ac));
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|
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/*
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* Create a table describing the layout of the CPU Extended
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* Save Area.
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*/
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if (use_xsave) {
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if (xsave_mask >> 32 != 0)
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max_ext_n = fls(xsave_mask >> 32) + 32;
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else
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max_ext_n = fls(xsave_mask);
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xsave_area_desc = malloc(max_ext_n * sizeof(struct
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xsave_area_elm_descr), M_DEVBUF, M_WAITOK | M_ZERO);
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/* x87 state */
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xsave_area_desc[0].offset = 0;
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xsave_area_desc[0].size = 160;
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/* XMM */
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xsave_area_desc[1].offset = 160;
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xsave_area_desc[1].size = 288 - 160;
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for (i = 2; i < max_ext_n; i++) {
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cpuid_count(0xd, i, cp);
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xsave_area_desc[i].offset = cp[1];
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xsave_area_desc[i].size = cp[0];
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}
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}
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|
|
fpu_save_area_zone = uma_zcreate("FPU_save_area",
|
|
cpu_max_ext_state_size, NULL, NULL, NULL, NULL,
|
|
XSAVE_AREA_ALIGN - 1, 0);
|
|
|
|
start_emulating();
|
|
intr_restore(saveintr);
|
|
}
|
|
SYSINIT(npxinitstate, SI_SUB_DRIVERS, SI_ORDER_ANY, npxinitstate, NULL);
|
|
|
|
/*
|
|
* Free coprocessor (if we have it).
|
|
*/
|
|
void
|
|
npxexit(struct thread *td)
|
|
{
|
|
|
|
critical_enter();
|
|
if (curthread == PCPU_GET(fpcurthread)) {
|
|
stop_emulating();
|
|
fpusave(curpcb->pcb_save);
|
|
start_emulating();
|
|
PCPU_SET(fpcurthread, NULL);
|
|
}
|
|
critical_exit();
|
|
#ifdef NPX_DEBUG
|
|
if (hw_float) {
|
|
u_int masked_exceptions;
|
|
|
|
masked_exceptions = GET_FPU_CW(td) & GET_FPU_SW(td) & 0x7f;
|
|
/*
|
|
* Log exceptions that would have trapped with the old
|
|
* control word (overflow, divide by 0, and invalid operand).
|
|
*/
|
|
if (masked_exceptions & 0x0d)
|
|
log(LOG_ERR,
|
|
"pid %d (%s) exited with masked floating point exceptions 0x%02x\n",
|
|
td->td_proc->p_pid, td->td_proc->p_comm,
|
|
masked_exceptions);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
int
|
|
npxformat(void)
|
|
{
|
|
|
|
if (!hw_float)
|
|
return (_MC_FPFMT_NODEV);
|
|
if (cpu_fxsr)
|
|
return (_MC_FPFMT_XMM);
|
|
return (_MC_FPFMT_387);
|
|
}
|
|
|
|
/*
|
|
* The following mechanism is used to ensure that the FPE_... value
|
|
* that is passed as a trapcode to the signal handler of the user
|
|
* process does not have more than one bit set.
|
|
*
|
|
* Multiple bits may be set if the user process modifies the control
|
|
* word while a status word bit is already set. While this is a sign
|
|
* of bad coding, we have no choise than to narrow them down to one
|
|
* bit, since we must not send a trapcode that is not exactly one of
|
|
* the FPE_ macros.
|
|
*
|
|
* The mechanism has a static table with 127 entries. Each combination
|
|
* of the 7 FPU status word exception bits directly translates to a
|
|
* position in this table, where a single FPE_... value is stored.
|
|
* This FPE_... value stored there is considered the "most important"
|
|
* of the exception bits and will be sent as the signal code. The
|
|
* precedence of the bits is based upon Intel Document "Numerical
|
|
* Applications", Chapter "Special Computational Situations".
|
|
*
|
|
* The macro to choose one of these values does these steps: 1) Throw
|
|
* away status word bits that cannot be masked. 2) Throw away the bits
|
|
* currently masked in the control word, assuming the user isn't
|
|
* interested in them anymore. 3) Reinsert status word bit 7 (stack
|
|
* fault) if it is set, which cannot be masked but must be presered.
|
|
* 4) Use the remaining bits to point into the trapcode table.
|
|
*
|
|
* The 6 maskable bits in order of their preference, as stated in the
|
|
* above referenced Intel manual:
|
|
* 1 Invalid operation (FP_X_INV)
|
|
* 1a Stack underflow
|
|
* 1b Stack overflow
|
|
* 1c Operand of unsupported format
|
|
* 1d SNaN operand.
|
|
* 2 QNaN operand (not an exception, irrelavant here)
|
|
* 3 Any other invalid-operation not mentioned above or zero divide
|
|
* (FP_X_INV, FP_X_DZ)
|
|
* 4 Denormal operand (FP_X_DNML)
|
|
* 5 Numeric over/underflow (FP_X_OFL, FP_X_UFL)
|
|
* 6 Inexact result (FP_X_IMP)
|
|
*/
|
|
static char fpetable[128] = {
|
|
0,
|
|
FPE_FLTINV, /* 1 - INV */
|
|
FPE_FLTUND, /* 2 - DNML */
|
|
FPE_FLTINV, /* 3 - INV | DNML */
|
|
FPE_FLTDIV, /* 4 - DZ */
|
|
FPE_FLTINV, /* 5 - INV | DZ */
|
|
FPE_FLTDIV, /* 6 - DNML | DZ */
|
|
FPE_FLTINV, /* 7 - INV | DNML | DZ */
|
|
FPE_FLTOVF, /* 8 - OFL */
|
|
FPE_FLTINV, /* 9 - INV | OFL */
|
|
FPE_FLTUND, /* A - DNML | OFL */
|
|
FPE_FLTINV, /* B - INV | DNML | OFL */
|
|
FPE_FLTDIV, /* C - DZ | OFL */
|
|
FPE_FLTINV, /* D - INV | DZ | OFL */
|
|
FPE_FLTDIV, /* E - DNML | DZ | OFL */
|
|
FPE_FLTINV, /* F - INV | DNML | DZ | OFL */
|
|
FPE_FLTUND, /* 10 - UFL */
|
|
FPE_FLTINV, /* 11 - INV | UFL */
|
|
FPE_FLTUND, /* 12 - DNML | UFL */
|
|
FPE_FLTINV, /* 13 - INV | DNML | UFL */
|
|
FPE_FLTDIV, /* 14 - DZ | UFL */
|
|
FPE_FLTINV, /* 15 - INV | DZ | UFL */
|
|
FPE_FLTDIV, /* 16 - DNML | DZ | UFL */
|
|
FPE_FLTINV, /* 17 - INV | DNML | DZ | UFL */
|
|
FPE_FLTOVF, /* 18 - OFL | UFL */
|
|
FPE_FLTINV, /* 19 - INV | OFL | UFL */
|
|
FPE_FLTUND, /* 1A - DNML | OFL | UFL */
|
|
FPE_FLTINV, /* 1B - INV | DNML | OFL | UFL */
|
|
FPE_FLTDIV, /* 1C - DZ | OFL | UFL */
|
|
FPE_FLTINV, /* 1D - INV | DZ | OFL | UFL */
|
|
FPE_FLTDIV, /* 1E - DNML | DZ | OFL | UFL */
|
|
FPE_FLTINV, /* 1F - INV | DNML | DZ | OFL | UFL */
|
|
FPE_FLTRES, /* 20 - IMP */
|
|
FPE_FLTINV, /* 21 - INV | IMP */
|
|
FPE_FLTUND, /* 22 - DNML | IMP */
|
|
FPE_FLTINV, /* 23 - INV | DNML | IMP */
|
|
FPE_FLTDIV, /* 24 - DZ | IMP */
|
|
FPE_FLTINV, /* 25 - INV | DZ | IMP */
|
|
FPE_FLTDIV, /* 26 - DNML | DZ | IMP */
|
|
FPE_FLTINV, /* 27 - INV | DNML | DZ | IMP */
|
|
FPE_FLTOVF, /* 28 - OFL | IMP */
|
|
FPE_FLTINV, /* 29 - INV | OFL | IMP */
|
|
FPE_FLTUND, /* 2A - DNML | OFL | IMP */
|
|
FPE_FLTINV, /* 2B - INV | DNML | OFL | IMP */
|
|
FPE_FLTDIV, /* 2C - DZ | OFL | IMP */
|
|
FPE_FLTINV, /* 2D - INV | DZ | OFL | IMP */
|
|
FPE_FLTDIV, /* 2E - DNML | DZ | OFL | IMP */
|
|
FPE_FLTINV, /* 2F - INV | DNML | DZ | OFL | IMP */
|
|
FPE_FLTUND, /* 30 - UFL | IMP */
|
|
FPE_FLTINV, /* 31 - INV | UFL | IMP */
|
|
FPE_FLTUND, /* 32 - DNML | UFL | IMP */
|
|
FPE_FLTINV, /* 33 - INV | DNML | UFL | IMP */
|
|
FPE_FLTDIV, /* 34 - DZ | UFL | IMP */
|
|
FPE_FLTINV, /* 35 - INV | DZ | UFL | IMP */
|
|
FPE_FLTDIV, /* 36 - DNML | DZ | UFL | IMP */
|
|
FPE_FLTINV, /* 37 - INV | DNML | DZ | UFL | IMP */
|
|
FPE_FLTOVF, /* 38 - OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 39 - INV | OFL | UFL | IMP */
|
|
FPE_FLTUND, /* 3A - DNML | OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 3B - INV | DNML | OFL | UFL | IMP */
|
|
FPE_FLTDIV, /* 3C - DZ | OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 3D - INV | DZ | OFL | UFL | IMP */
|
|
FPE_FLTDIV, /* 3E - DNML | DZ | OFL | UFL | IMP */
|
|
FPE_FLTINV, /* 3F - INV | DNML | DZ | OFL | UFL | IMP */
|
|
FPE_FLTSUB, /* 40 - STK */
|
|
FPE_FLTSUB, /* 41 - INV | STK */
|
|
FPE_FLTUND, /* 42 - DNML | STK */
|
|
FPE_FLTSUB, /* 43 - INV | DNML | STK */
|
|
FPE_FLTDIV, /* 44 - DZ | STK */
|
|
FPE_FLTSUB, /* 45 - INV | DZ | STK */
|
|
FPE_FLTDIV, /* 46 - DNML | DZ | STK */
|
|
FPE_FLTSUB, /* 47 - INV | DNML | DZ | STK */
|
|
FPE_FLTOVF, /* 48 - OFL | STK */
|
|
FPE_FLTSUB, /* 49 - INV | OFL | STK */
|
|
FPE_FLTUND, /* 4A - DNML | OFL | STK */
|
|
FPE_FLTSUB, /* 4B - INV | DNML | OFL | STK */
|
|
FPE_FLTDIV, /* 4C - DZ | OFL | STK */
|
|
FPE_FLTSUB, /* 4D - INV | DZ | OFL | STK */
|
|
FPE_FLTDIV, /* 4E - DNML | DZ | OFL | STK */
|
|
FPE_FLTSUB, /* 4F - INV | DNML | DZ | OFL | STK */
|
|
FPE_FLTUND, /* 50 - UFL | STK */
|
|
FPE_FLTSUB, /* 51 - INV | UFL | STK */
|
|
FPE_FLTUND, /* 52 - DNML | UFL | STK */
|
|
FPE_FLTSUB, /* 53 - INV | DNML | UFL | STK */
|
|
FPE_FLTDIV, /* 54 - DZ | UFL | STK */
|
|
FPE_FLTSUB, /* 55 - INV | DZ | UFL | STK */
|
|
FPE_FLTDIV, /* 56 - DNML | DZ | UFL | STK */
|
|
FPE_FLTSUB, /* 57 - INV | DNML | DZ | UFL | STK */
|
|
FPE_FLTOVF, /* 58 - OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 59 - INV | OFL | UFL | STK */
|
|
FPE_FLTUND, /* 5A - DNML | OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 5B - INV | DNML | OFL | UFL | STK */
|
|
FPE_FLTDIV, /* 5C - DZ | OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 5D - INV | DZ | OFL | UFL | STK */
|
|
FPE_FLTDIV, /* 5E - DNML | DZ | OFL | UFL | STK */
|
|
FPE_FLTSUB, /* 5F - INV | DNML | DZ | OFL | UFL | STK */
|
|
FPE_FLTRES, /* 60 - IMP | STK */
|
|
FPE_FLTSUB, /* 61 - INV | IMP | STK */
|
|
FPE_FLTUND, /* 62 - DNML | IMP | STK */
|
|
FPE_FLTSUB, /* 63 - INV | DNML | IMP | STK */
|
|
FPE_FLTDIV, /* 64 - DZ | IMP | STK */
|
|
FPE_FLTSUB, /* 65 - INV | DZ | IMP | STK */
|
|
FPE_FLTDIV, /* 66 - DNML | DZ | IMP | STK */
|
|
FPE_FLTSUB, /* 67 - INV | DNML | DZ | IMP | STK */
|
|
FPE_FLTOVF, /* 68 - OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 69 - INV | OFL | IMP | STK */
|
|
FPE_FLTUND, /* 6A - DNML | OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 6B - INV | DNML | OFL | IMP | STK */
|
|
FPE_FLTDIV, /* 6C - DZ | OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 6D - INV | DZ | OFL | IMP | STK */
|
|
FPE_FLTDIV, /* 6E - DNML | DZ | OFL | IMP | STK */
|
|
FPE_FLTSUB, /* 6F - INV | DNML | DZ | OFL | IMP | STK */
|
|
FPE_FLTUND, /* 70 - UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 71 - INV | UFL | IMP | STK */
|
|
FPE_FLTUND, /* 72 - DNML | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 73 - INV | DNML | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 74 - DZ | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 75 - INV | DZ | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 76 - DNML | DZ | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 77 - INV | DNML | DZ | UFL | IMP | STK */
|
|
FPE_FLTOVF, /* 78 - OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 79 - INV | OFL | UFL | IMP | STK */
|
|
FPE_FLTUND, /* 7A - DNML | OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 7B - INV | DNML | OFL | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 7C - DZ | OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 7D - INV | DZ | OFL | UFL | IMP | STK */
|
|
FPE_FLTDIV, /* 7E - DNML | DZ | OFL | UFL | IMP | STK */
|
|
FPE_FLTSUB, /* 7F - INV | DNML | DZ | OFL | UFL | IMP | STK */
|
|
};
|
|
|
|
/*
|
|
* Read the FP status and control words, then generate si_code value
|
|
* for SIGFPE. The error code chosen will be one of the
|
|
* FPE_... macros. It will be sent as the second argument to old
|
|
* BSD-style signal handlers and as "siginfo_t->si_code" (second
|
|
* argument) to SA_SIGINFO signal handlers.
|
|
*
|
|
* Some time ago, we cleared the x87 exceptions with FNCLEX there.
|
|
* Clearing exceptions was necessary mainly to avoid IRQ13 bugs. The
|
|
* usermode code which understands the FPU hardware enough to enable
|
|
* the exceptions, can also handle clearing the exception state in the
|
|
* handler. The only consequence of not clearing the exception is the
|
|
* rethrow of the SIGFPE on return from the signal handler and
|
|
* reexecution of the corresponding instruction.
|
|
*
|
|
* For XMM traps, the exceptions were never cleared.
|
|
*/
|
|
int
|
|
npxtrap_x87(void)
|
|
{
|
|
u_short control, status;
|
|
|
|
if (!hw_float) {
|
|
printf(
|
|
"npxtrap_x87: fpcurthread = %p, curthread = %p, hw_float = %d\n",
|
|
PCPU_GET(fpcurthread), curthread, hw_float);
|
|
panic("npxtrap from nowhere");
|
|
}
|
|
critical_enter();
|
|
|
|
/*
|
|
* Interrupt handling (for another interrupt) may have pushed the
|
|
* state to memory. Fetch the relevant parts of the state from
|
|
* wherever they are.
|
|
*/
|
|
if (PCPU_GET(fpcurthread) != curthread) {
|
|
control = GET_FPU_CW(curthread);
|
|
status = GET_FPU_SW(curthread);
|
|
} else {
|
|
fnstcw(&control);
|
|
fnstsw(&status);
|
|
}
|
|
critical_exit();
|
|
return (fpetable[status & ((~control & 0x3f) | 0x40)]);
|
|
}
|
|
|
|
int
|
|
npxtrap_sse(void)
|
|
{
|
|
u_int mxcsr;
|
|
|
|
if (!hw_float) {
|
|
printf(
|
|
"npxtrap_sse: fpcurthread = %p, curthread = %p, hw_float = %d\n",
|
|
PCPU_GET(fpcurthread), curthread, hw_float);
|
|
panic("npxtrap from nowhere");
|
|
}
|
|
critical_enter();
|
|
if (PCPU_GET(fpcurthread) != curthread)
|
|
mxcsr = curthread->td_pcb->pcb_save->sv_xmm.sv_env.en_mxcsr;
|
|
else
|
|
stmxcsr(&mxcsr);
|
|
critical_exit();
|
|
return (fpetable[(mxcsr & (~mxcsr >> 7)) & 0x3f]);
|
|
}
|
|
|
|
/*
|
|
* Implement device not available (DNA) exception
|
|
*
|
|
* It would be better to switch FP context here (if curthread != fpcurthread)
|
|
* and not necessarily for every context switch, but it is too hard to
|
|
* access foreign pcb's.
|
|
*/
|
|
|
|
static int err_count = 0;
|
|
|
|
int
|
|
npxdna(void)
|
|
{
|
|
|
|
if (!hw_float)
|
|
return (0);
|
|
critical_enter();
|
|
if (PCPU_GET(fpcurthread) == curthread) {
|
|
printf("npxdna: fpcurthread == curthread %d times\n",
|
|
++err_count);
|
|
stop_emulating();
|
|
critical_exit();
|
|
return (1);
|
|
}
|
|
if (PCPU_GET(fpcurthread) != NULL) {
|
|
printf("npxdna: fpcurthread = %p (%d), curthread = %p (%d)\n",
|
|
PCPU_GET(fpcurthread),
|
|
PCPU_GET(fpcurthread)->td_proc->p_pid,
|
|
curthread, curthread->td_proc->p_pid);
|
|
panic("npxdna");
|
|
}
|
|
stop_emulating();
|
|
/*
|
|
* Record new context early in case frstor causes a trap.
|
|
*/
|
|
PCPU_SET(fpcurthread, curthread);
|
|
|
|
if (cpu_fxsr)
|
|
fpu_clean_state();
|
|
|
|
if ((curpcb->pcb_flags & PCB_NPXINITDONE) == 0) {
|
|
/*
|
|
* This is the first time this thread has used the FPU or
|
|
* the PCB doesn't contain a clean FPU state. Explicitly
|
|
* load an initial state.
|
|
*
|
|
* We prefer to restore the state from the actual save
|
|
* area in PCB instead of directly loading from
|
|
* npx_initialstate, to ignite the XSAVEOPT
|
|
* tracking engine.
|
|
*/
|
|
bcopy(npx_initialstate, curpcb->pcb_save, cpu_max_ext_state_size);
|
|
fpurstor(curpcb->pcb_save);
|
|
if (curpcb->pcb_initial_npxcw != __INITIAL_NPXCW__)
|
|
fldcw(curpcb->pcb_initial_npxcw);
|
|
curpcb->pcb_flags |= PCB_NPXINITDONE;
|
|
if (PCB_USER_FPU(curpcb))
|
|
curpcb->pcb_flags |= PCB_NPXUSERINITDONE;
|
|
} else {
|
|
fpurstor(curpcb->pcb_save);
|
|
}
|
|
critical_exit();
|
|
|
|
return (1);
|
|
}
|
|
|
|
/*
|
|
* Wrapper for fpusave() called from context switch routines.
|
|
*
|
|
* npxsave() must be called with interrupts disabled, so that it clears
|
|
* fpcurthread atomically with saving the state. We require callers to do the
|
|
* disabling, since most callers need to disable interrupts anyway to call
|
|
* npxsave() atomically with checking fpcurthread.
|
|
*/
|
|
void
|
|
npxsave(addr)
|
|
union savefpu *addr;
|
|
{
|
|
|
|
stop_emulating();
|
|
if (use_xsaveopt)
|
|
xsaveopt((char *)addr, xsave_mask);
|
|
else
|
|
fpusave(addr);
|
|
start_emulating();
|
|
PCPU_SET(fpcurthread, NULL);
|
|
}
|
|
|
|
/*
|
|
* Unconditionally save the current co-processor state across suspend and
|
|
* resume.
|
|
*/
|
|
void
|
|
npxsuspend(union savefpu *addr)
|
|
{
|
|
register_t cr0;
|
|
|
|
if (!hw_float)
|
|
return;
|
|
if (PCPU_GET(fpcurthread) == NULL) {
|
|
bcopy(npx_initialstate, addr, cpu_max_ext_state_size);
|
|
return;
|
|
}
|
|
cr0 = rcr0();
|
|
stop_emulating();
|
|
fpusave(addr);
|
|
load_cr0(cr0);
|
|
}
|
|
|
|
void
|
|
npxresume(union savefpu *addr)
|
|
{
|
|
register_t cr0;
|
|
|
|
if (!hw_float)
|
|
return;
|
|
|
|
cr0 = rcr0();
|
|
npxinit(false);
|
|
stop_emulating();
|
|
fpurstor(addr);
|
|
load_cr0(cr0);
|
|
}
|
|
|
|
void
|
|
npxdrop(void)
|
|
{
|
|
struct thread *td;
|
|
|
|
/*
|
|
* Discard pending exceptions in the !cpu_fxsr case so that unmasked
|
|
* ones don't cause a panic on the next frstor.
|
|
*/
|
|
if (!cpu_fxsr)
|
|
fnclex();
|
|
|
|
td = PCPU_GET(fpcurthread);
|
|
KASSERT(td == curthread, ("fpudrop: fpcurthread != curthread"));
|
|
CRITICAL_ASSERT(td);
|
|
PCPU_SET(fpcurthread, NULL);
|
|
td->td_pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
start_emulating();
|
|
}
|
|
|
|
/*
|
|
* Get the user state of the FPU into pcb->pcb_user_save without
|
|
* dropping ownership (if possible). It returns the FPU ownership
|
|
* status.
|
|
*/
|
|
int
|
|
npxgetregs(struct thread *td)
|
|
{
|
|
struct pcb *pcb;
|
|
uint64_t *xstate_bv, bit;
|
|
char *sa;
|
|
int max_ext_n, i;
|
|
int owned;
|
|
|
|
if (!hw_float)
|
|
return (_MC_FPOWNED_NONE);
|
|
|
|
pcb = td->td_pcb;
|
|
if ((pcb->pcb_flags & PCB_NPXINITDONE) == 0) {
|
|
bcopy(npx_initialstate, get_pcb_user_save_pcb(pcb),
|
|
cpu_max_ext_state_size);
|
|
SET_FPU_CW(get_pcb_user_save_pcb(pcb), pcb->pcb_initial_npxcw);
|
|
npxuserinited(td);
|
|
return (_MC_FPOWNED_PCB);
|
|
}
|
|
critical_enter();
|
|
if (td == PCPU_GET(fpcurthread)) {
|
|
fpusave(get_pcb_user_save_pcb(pcb));
|
|
if (!cpu_fxsr)
|
|
/*
|
|
* fnsave initializes the FPU and destroys whatever
|
|
* context it contains. Make sure the FPU owner
|
|
* starts with a clean state next time.
|
|
*/
|
|
npxdrop();
|
|
owned = _MC_FPOWNED_FPU;
|
|
} else {
|
|
owned = _MC_FPOWNED_PCB;
|
|
}
|
|
critical_exit();
|
|
if (use_xsave) {
|
|
/*
|
|
* Handle partially saved state.
|
|
*/
|
|
sa = (char *)get_pcb_user_save_pcb(pcb);
|
|
xstate_bv = (uint64_t *)(sa + sizeof(union savefpu) +
|
|
offsetof(struct xstate_hdr, xstate_bv));
|
|
if (xsave_mask >> 32 != 0)
|
|
max_ext_n = fls(xsave_mask >> 32) + 32;
|
|
else
|
|
max_ext_n = fls(xsave_mask);
|
|
for (i = 0; i < max_ext_n; i++) {
|
|
bit = 1ULL << i;
|
|
if ((xsave_mask & bit) == 0 || (*xstate_bv & bit) != 0)
|
|
continue;
|
|
bcopy((char *)npx_initialstate +
|
|
xsave_area_desc[i].offset,
|
|
sa + xsave_area_desc[i].offset,
|
|
xsave_area_desc[i].size);
|
|
*xstate_bv |= bit;
|
|
}
|
|
}
|
|
return (owned);
|
|
}
|
|
|
|
void
|
|
npxuserinited(struct thread *td)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
pcb = td->td_pcb;
|
|
if (PCB_USER_FPU(pcb))
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
pcb->pcb_flags |= PCB_NPXUSERINITDONE;
|
|
}
|
|
|
|
int
|
|
npxsetxstate(struct thread *td, char *xfpustate, size_t xfpustate_size)
|
|
{
|
|
struct xstate_hdr *hdr, *ehdr;
|
|
size_t len, max_len;
|
|
uint64_t bv;
|
|
|
|
/* XXXKIB should we clear all extended state in xstate_bv instead ? */
|
|
if (xfpustate == NULL)
|
|
return (0);
|
|
if (!use_xsave)
|
|
return (EOPNOTSUPP);
|
|
|
|
len = xfpustate_size;
|
|
if (len < sizeof(struct xstate_hdr))
|
|
return (EINVAL);
|
|
max_len = cpu_max_ext_state_size - sizeof(union savefpu);
|
|
if (len > max_len)
|
|
return (EINVAL);
|
|
|
|
ehdr = (struct xstate_hdr *)xfpustate;
|
|
bv = ehdr->xstate_bv;
|
|
|
|
/*
|
|
* Avoid #gp.
|
|
*/
|
|
if (bv & ~xsave_mask)
|
|
return (EINVAL);
|
|
|
|
hdr = (struct xstate_hdr *)(get_pcb_user_save_td(td) + 1);
|
|
|
|
hdr->xstate_bv = bv;
|
|
bcopy(xfpustate + sizeof(struct xstate_hdr),
|
|
(char *)(hdr + 1), len - sizeof(struct xstate_hdr));
|
|
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
npxsetregs(struct thread *td, union savefpu *addr, char *xfpustate,
|
|
size_t xfpustate_size)
|
|
{
|
|
struct pcb *pcb;
|
|
int error;
|
|
|
|
if (!hw_float)
|
|
return (ENXIO);
|
|
|
|
pcb = td->td_pcb;
|
|
critical_enter();
|
|
if (td == PCPU_GET(fpcurthread) && PCB_USER_FPU(pcb)) {
|
|
error = npxsetxstate(td, xfpustate, xfpustate_size);
|
|
if (error != 0) {
|
|
critical_exit();
|
|
return (error);
|
|
}
|
|
if (!cpu_fxsr)
|
|
fnclex(); /* As in npxdrop(). */
|
|
bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
|
|
fpurstor(get_pcb_user_save_td(td));
|
|
critical_exit();
|
|
pcb->pcb_flags |= PCB_NPXUSERINITDONE | PCB_NPXINITDONE;
|
|
} else {
|
|
critical_exit();
|
|
error = npxsetxstate(td, xfpustate, xfpustate_size);
|
|
if (error != 0)
|
|
return (error);
|
|
bcopy(addr, get_pcb_user_save_td(td), sizeof(*addr));
|
|
npxuserinited(td);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
fpusave(addr)
|
|
union savefpu *addr;
|
|
{
|
|
|
|
if (use_xsave)
|
|
xsave((char *)addr, xsave_mask);
|
|
else if (cpu_fxsr)
|
|
fxsave(addr);
|
|
else
|
|
fnsave(addr);
|
|
}
|
|
|
|
static void
|
|
npx_fill_fpregs_xmm1(struct savexmm *sv_xmm, struct save87 *sv_87)
|
|
{
|
|
struct env87 *penv_87;
|
|
struct envxmm *penv_xmm;
|
|
int i;
|
|
|
|
penv_87 = &sv_87->sv_env;
|
|
penv_xmm = &sv_xmm->sv_env;
|
|
|
|
/* FPU control/status */
|
|
penv_87->en_cw = penv_xmm->en_cw;
|
|
penv_87->en_sw = penv_xmm->en_sw;
|
|
penv_87->en_fip = penv_xmm->en_fip;
|
|
penv_87->en_fcs = penv_xmm->en_fcs;
|
|
penv_87->en_opcode = penv_xmm->en_opcode;
|
|
penv_87->en_foo = penv_xmm->en_foo;
|
|
penv_87->en_fos = penv_xmm->en_fos;
|
|
|
|
/* FPU registers and tags */
|
|
penv_87->en_tw = 0xffff;
|
|
for (i = 0; i < 8; ++i) {
|
|
sv_87->sv_ac[i] = sv_xmm->sv_fp[i].fp_acc;
|
|
if ((penv_xmm->en_tw & (1 << i)) != 0)
|
|
/* zero and special are set as valid */
|
|
penv_87->en_tw &= ~(3 << i * 2);
|
|
}
|
|
}
|
|
|
|
void
|
|
npx_fill_fpregs_xmm(struct savexmm *sv_xmm, struct save87 *sv_87)
|
|
{
|
|
|
|
bzero(sv_87, sizeof(*sv_87));
|
|
npx_fill_fpregs_xmm1(sv_xmm, sv_87);
|
|
}
|
|
|
|
void
|
|
npx_set_fpregs_xmm(struct save87 *sv_87, struct savexmm *sv_xmm)
|
|
{
|
|
struct env87 *penv_87;
|
|
struct envxmm *penv_xmm;
|
|
int i;
|
|
|
|
penv_87 = &sv_87->sv_env;
|
|
penv_xmm = &sv_xmm->sv_env;
|
|
|
|
/* FPU control/status */
|
|
penv_xmm->en_cw = penv_87->en_cw;
|
|
penv_xmm->en_sw = penv_87->en_sw;
|
|
penv_xmm->en_fip = penv_87->en_fip;
|
|
penv_xmm->en_fcs = penv_87->en_fcs;
|
|
penv_xmm->en_opcode = penv_87->en_opcode;
|
|
penv_xmm->en_foo = penv_87->en_foo;
|
|
penv_xmm->en_fos = penv_87->en_fos;
|
|
|
|
/*
|
|
* FPU registers and tags.
|
|
* Abridged / Full translation (values in binary), see FXSAVE spec.
|
|
* 0 11
|
|
* 1 00, 01, 10
|
|
*/
|
|
penv_xmm->en_tw = 0;
|
|
for (i = 0; i < 8; ++i) {
|
|
sv_xmm->sv_fp[i].fp_acc = sv_87->sv_ac[i];
|
|
if ((penv_87->en_tw & (3 << i * 2)) != (3 << i * 2))
|
|
penv_xmm->en_tw |= 1 << i;
|
|
}
|
|
}
|
|
|
|
void
|
|
npx_get_fsave(void *addr)
|
|
{
|
|
struct thread *td;
|
|
union savefpu *sv;
|
|
|
|
td = curthread;
|
|
npxgetregs(td);
|
|
sv = get_pcb_user_save_td(td);
|
|
if (cpu_fxsr)
|
|
npx_fill_fpregs_xmm1(&sv->sv_xmm, addr);
|
|
else
|
|
bcopy(sv, addr, sizeof(struct env87) +
|
|
sizeof(struct fpacc87[8]));
|
|
}
|
|
|
|
int
|
|
npx_set_fsave(void *addr)
|
|
{
|
|
union savefpu sv;
|
|
int error;
|
|
|
|
bzero(&sv, sizeof(sv));
|
|
if (cpu_fxsr)
|
|
npx_set_fpregs_xmm(addr, &sv.sv_xmm);
|
|
else
|
|
bcopy(addr, &sv, sizeof(struct env87) +
|
|
sizeof(struct fpacc87[8]));
|
|
error = npxsetregs(curthread, &sv, NULL, 0);
|
|
return (error);
|
|
}
|
|
|
|
/*
|
|
* On AuthenticAMD processors, the fxrstor instruction does not restore
|
|
* the x87's stored last instruction pointer, last data pointer, and last
|
|
* opcode values, except in the rare case in which the exception summary
|
|
* (ES) bit in the x87 status word is set to 1.
|
|
*
|
|
* In order to avoid leaking this information across processes, we clean
|
|
* these values by performing a dummy load before executing fxrstor().
|
|
*/
|
|
static void
|
|
fpu_clean_state(void)
|
|
{
|
|
static float dummy_variable = 0.0;
|
|
u_short status;
|
|
|
|
/*
|
|
* Clear the ES bit in the x87 status word if it is currently
|
|
* set, in order to avoid causing a fault in the upcoming load.
|
|
*/
|
|
fnstsw(&status);
|
|
if (status & 0x80)
|
|
fnclex();
|
|
|
|
/*
|
|
* Load the dummy variable into the x87 stack. This mangles
|
|
* the x87 stack, but we don't care since we're about to call
|
|
* fxrstor() anyway.
|
|
*/
|
|
__asm __volatile("ffree %%st(7); flds %0" : : "m" (dummy_variable));
|
|
}
|
|
|
|
static void
|
|
fpurstor(union savefpu *addr)
|
|
{
|
|
|
|
if (use_xsave)
|
|
xrstor((char *)addr, xsave_mask);
|
|
else if (cpu_fxsr)
|
|
fxrstor(addr);
|
|
else
|
|
frstor(addr);
|
|
}
|
|
|
|
#ifdef DEV_ISA
|
|
/*
|
|
* This sucks up the legacy ISA support assignments from PNPBIOS/ACPI.
|
|
*/
|
|
static struct isa_pnp_id npxisa_ids[] = {
|
|
{ 0x040cd041, "Legacy ISA coprocessor support" }, /* PNP0C04 */
|
|
{ 0 }
|
|
};
|
|
|
|
static int
|
|
npxisa_probe(device_t dev)
|
|
{
|
|
int result;
|
|
if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, npxisa_ids)) <= 0) {
|
|
device_quiet(dev);
|
|
}
|
|
return(result);
|
|
}
|
|
|
|
static int
|
|
npxisa_attach(device_t dev)
|
|
{
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t npxisa_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, npxisa_probe),
|
|
DEVMETHOD(device_attach, npxisa_attach),
|
|
DEVMETHOD(device_detach, bus_generic_detach),
|
|
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
|
DEVMETHOD(device_suspend, bus_generic_suspend),
|
|
DEVMETHOD(device_resume, bus_generic_resume),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t npxisa_driver = {
|
|
"npxisa",
|
|
npxisa_methods,
|
|
1, /* no softc */
|
|
};
|
|
|
|
static devclass_t npxisa_devclass;
|
|
|
|
DRIVER_MODULE(npxisa, isa, npxisa_driver, npxisa_devclass, 0, 0);
|
|
DRIVER_MODULE(npxisa, acpi, npxisa_driver, npxisa_devclass, 0, 0);
|
|
#endif /* DEV_ISA */
|
|
|
|
static MALLOC_DEFINE(M_FPUKERN_CTX, "fpukern_ctx",
|
|
"Kernel contexts for FPU state");
|
|
|
|
#define FPU_KERN_CTX_NPXINITDONE 0x01
|
|
#define FPU_KERN_CTX_DUMMY 0x02
|
|
#define FPU_KERN_CTX_INUSE 0x04
|
|
|
|
struct fpu_kern_ctx {
|
|
union savefpu *prev;
|
|
uint32_t flags;
|
|
char hwstate1[];
|
|
};
|
|
|
|
struct fpu_kern_ctx *
|
|
fpu_kern_alloc_ctx(u_int flags)
|
|
{
|
|
struct fpu_kern_ctx *res;
|
|
size_t sz;
|
|
|
|
sz = sizeof(struct fpu_kern_ctx) + XSAVE_AREA_ALIGN +
|
|
cpu_max_ext_state_size;
|
|
res = malloc(sz, M_FPUKERN_CTX, ((flags & FPU_KERN_NOWAIT) ?
|
|
M_NOWAIT : M_WAITOK) | M_ZERO);
|
|
return (res);
|
|
}
|
|
|
|
void
|
|
fpu_kern_free_ctx(struct fpu_kern_ctx *ctx)
|
|
{
|
|
|
|
KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("free'ing inuse ctx"));
|
|
/* XXXKIB clear the memory ? */
|
|
free(ctx, M_FPUKERN_CTX);
|
|
}
|
|
|
|
static union savefpu *
|
|
fpu_kern_ctx_savefpu(struct fpu_kern_ctx *ctx)
|
|
{
|
|
vm_offset_t p;
|
|
|
|
p = (vm_offset_t)&ctx->hwstate1;
|
|
p = roundup2(p, XSAVE_AREA_ALIGN);
|
|
return ((union savefpu *)p);
|
|
}
|
|
|
|
int
|
|
fpu_kern_enter(struct thread *td, struct fpu_kern_ctx *ctx, u_int flags)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) == 0, ("using inuse ctx"));
|
|
|
|
if ((flags & FPU_KERN_KTHR) != 0 && is_fpu_kern_thread(0)) {
|
|
ctx->flags = FPU_KERN_CTX_DUMMY | FPU_KERN_CTX_INUSE;
|
|
return (0);
|
|
}
|
|
pcb = td->td_pcb;
|
|
KASSERT(!PCB_USER_FPU(pcb) || pcb->pcb_save ==
|
|
get_pcb_user_save_pcb(pcb), ("mangled pcb_save"));
|
|
ctx->flags = FPU_KERN_CTX_INUSE;
|
|
if ((pcb->pcb_flags & PCB_NPXINITDONE) != 0)
|
|
ctx->flags |= FPU_KERN_CTX_NPXINITDONE;
|
|
npxexit(td);
|
|
ctx->prev = pcb->pcb_save;
|
|
pcb->pcb_save = fpu_kern_ctx_savefpu(ctx);
|
|
pcb->pcb_flags |= PCB_KERNNPX;
|
|
pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
fpu_kern_leave(struct thread *td, struct fpu_kern_ctx *ctx)
|
|
{
|
|
struct pcb *pcb;
|
|
|
|
KASSERT((ctx->flags & FPU_KERN_CTX_INUSE) != 0,
|
|
("leaving not inuse ctx"));
|
|
ctx->flags &= ~FPU_KERN_CTX_INUSE;
|
|
|
|
if (is_fpu_kern_thread(0) && (ctx->flags & FPU_KERN_CTX_DUMMY) != 0)
|
|
return (0);
|
|
pcb = td->td_pcb;
|
|
critical_enter();
|
|
if (curthread == PCPU_GET(fpcurthread))
|
|
npxdrop();
|
|
critical_exit();
|
|
pcb->pcb_save = ctx->prev;
|
|
if (pcb->pcb_save == get_pcb_user_save_pcb(pcb)) {
|
|
if ((pcb->pcb_flags & PCB_NPXUSERINITDONE) != 0)
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
else
|
|
pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
pcb->pcb_flags &= ~PCB_KERNNPX;
|
|
} else {
|
|
if ((ctx->flags & FPU_KERN_CTX_NPXINITDONE) != 0)
|
|
pcb->pcb_flags |= PCB_NPXINITDONE;
|
|
else
|
|
pcb->pcb_flags &= ~PCB_NPXINITDONE;
|
|
KASSERT(!PCB_USER_FPU(pcb), ("unpaired fpu_kern_leave"));
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
fpu_kern_thread(u_int flags)
|
|
{
|
|
|
|
KASSERT((curthread->td_pflags & TDP_KTHREAD) != 0,
|
|
("Only kthread may use fpu_kern_thread"));
|
|
KASSERT(curpcb->pcb_save == get_pcb_user_save_pcb(curpcb),
|
|
("mangled pcb_save"));
|
|
KASSERT(PCB_USER_FPU(curpcb), ("recursive call"));
|
|
|
|
curpcb->pcb_flags |= PCB_KERNNPX;
|
|
return (0);
|
|
}
|
|
|
|
int
|
|
is_fpu_kern_thread(u_int flags)
|
|
{
|
|
|
|
if ((curthread->td_pflags & TDP_KTHREAD) == 0)
|
|
return (0);
|
|
return ((curpcb->pcb_flags & PCB_KERNNPX) != 0);
|
|
}
|
|
|
|
/*
|
|
* FPU save area alloc/free/init utility routines
|
|
*/
|
|
union savefpu *
|
|
fpu_save_area_alloc(void)
|
|
{
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|
|
|
return (uma_zalloc(fpu_save_area_zone, 0));
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}
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|
|
|
void
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|
fpu_save_area_free(union savefpu *fsa)
|
|
{
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|
|
|
uma_zfree(fpu_save_area_zone, fsa);
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|
}
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|
|
|
void
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|
fpu_save_area_reset(union savefpu *fsa)
|
|
{
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|
|
|
bcopy(npx_initialstate, fsa, cpu_max_ext_state_size);
|
|
}
|