56248d9da8
make use of it where possible. This primarily brings in support for newer hardware, and FreeBSD is not yet able to support the abundance of IRQs on new hardware and many features in the Ethernet driver. Because of the changes to IRQs in the Simple Executive, we have to maintain our own list of Octeon IRQs now, which probably can be pared-down and be specific to the CIU interrupt unit soon, and when other interrupt mechanisms are added they can maintain their own definitions. Remove unmasking of interrupts from within the UART device now that the function used is no longer present in the Simple Executive. The unmasking seems to have been gratuitous as this is more properly handled by the buses above the UART device, and seems to work on that basis.
172 lines
5.3 KiB
C
172 lines
5.3 KiB
C
/***********************license start***************
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* Copyright (c) 2003-2010 Cavium Inc. (support@cavium.com). All rights
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* reserved.
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*
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Cavium Inc. nor the names of
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* its contributors may be used to endorse or promote products
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* derived from this software without specific prior written
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* permission.
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* This Software, including technical data, may be subject to U.S. export control
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* laws, including the U.S. Export Administration Act and its associated
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* regulations, and may be subject to export or import regulations in other
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* countries.
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* TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
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* AND WITH ALL FAULTS AND CAVIUM INC. MAKES NO PROMISES, REPRESENTATIONS OR
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* WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH RESPECT TO
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* THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY REPRESENTATION OR
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* DESCRIPTION, OR THE EXISTENCE OF ANY LATENT OR PATENT DEFECTS, AND CAVIUM
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* SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES OF TITLE,
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* MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR PURPOSE, LACK OF
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* VIRUSES, ACCURACY OR COMPLETENESS, QUIET ENJOYMENT, QUIET POSSESSION OR
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* CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT OF USE OR
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* PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
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***********************license end**************************************/
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/**
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* @file
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*
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* This file provides reader/writer locks.
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*
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* <hr>$Revision: 70030 $<hr>
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*
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*
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*/
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#ifndef __CVMX_RWLOCK_H__
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#define __CVMX_RWLOCK_H__
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/* include to get atomic compare and store */
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#include "cvmx-atomic.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Flags for lock value in rw lock structure */
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#define CVMX_RWLOCK_WRITE_FLAG 0x1
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#define CVMX_RWLOCK_READ_INC 0x2
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/* Writer preference locks (wp). Can be starved by writers. When a writer
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* is waiting, no readers are given the lock until all writers are done.
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*/
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typedef struct
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{
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volatile uint32_t lock;
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volatile uint32_t write_req;
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volatile uint32_t write_comp;
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} cvmx_rwlock_wp_lock_t;
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/**
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* Initialize a reader/writer lock. This must be done
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* by a single core before used.
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*
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* @param lock pointer to rwlock structure
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*/
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static inline void cvmx_rwlock_wp_init(cvmx_rwlock_wp_lock_t *lock)
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{
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lock->lock = 0;
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lock->write_req = 0;
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lock->write_comp = 0;
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}
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/**
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* Perform a reader lock. If a writer is pending, this
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* will wait for that writer to complete before locking.
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*
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* NOTE: Each thread/process must only lock any rwlock
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* once, or else a deadlock may result.
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*
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* @param lock pointer to rwlock structure
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*/
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static inline void cvmx_rwlock_wp_read_lock(cvmx_rwlock_wp_lock_t *lock)
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{
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/* Wait for outstanding write requests to be serviced */
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while (lock->write_req != lock->write_comp)
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;
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/* Add ourselves to interested reader count */
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cvmx_atomic_add32_nosync((int32_t *)&(lock->lock), CVMX_RWLOCK_READ_INC);
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/* Wait for writer to finish. No writer will start again
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** until after we are done since we have already incremented
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** the reader count
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*/
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while (lock->lock & CVMX_RWLOCK_WRITE_FLAG)
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;
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}
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/**
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* Perform a reader unlock.
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*
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* @param lock pointer to rwlock structure
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*/
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static inline void cvmx_rwlock_wp_read_unlock(cvmx_rwlock_wp_lock_t *lock)
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{
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/* Remove ourselves to reader count */
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cvmx_atomic_add32_nosync((int32_t *)&(lock->lock), -CVMX_RWLOCK_READ_INC);
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}
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/**
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* Perform a writer lock. Any readers that attempt
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* to get a lock while there are any pending write locks
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* will wait until all writers have completed. Starvation
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* of readers by writers is possible and must be avoided
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* by the application.
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*
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* @param lock pointer to rwlock structure
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*/
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static inline void cvmx_rwlock_wp_write_lock(cvmx_rwlock_wp_lock_t *lock)
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{
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/* Get previous value of write requests */
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uint32_t prev_writers = ((uint32_t)cvmx_atomic_fetch_and_add32((int32_t *)&(lock->write_req), 1));
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/* Spin until our turn */
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while (prev_writers != lock->write_comp)
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;
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/* Spin until no other readers or writers, then set write flag */
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while (!cvmx_atomic_compare_and_store32((uint32_t *)&(lock->lock), 0, CVMX_RWLOCK_WRITE_FLAG))
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;
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}
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/**
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* Perform a writer unlock.
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*
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* @param lock pointer to rwlock structure
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*/
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static inline void cvmx_rwlock_wp_write_unlock(cvmx_rwlock_wp_lock_t *lock)
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{
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/* Remove our writer flag */
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CVMX_SYNCWS; /* Make sure all writes in protected region are visible before unlock */
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cvmx_atomic_add32_nosync((int32_t *)&(lock->lock), -CVMX_RWLOCK_WRITE_FLAG);
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cvmx_atomic_add32_nosync((int32_t *)&(lock->write_comp), 1);
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CVMX_SYNCWS; /* push unlock writes out, but don't stall */
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CVMX_RWLOCK_H__ */
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