533 lines
18 KiB
Groff
533 lines
18 KiB
Groff
.\" Copyright (c) 2016-2017 The FreeBSD Foundation. All rights reserved.
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.\"
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.\" This documentation was created by Ed Maste under sponsorship of
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.\" The FreeBSD Foundation.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd November 20, 2019
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.Dt ARCH 7
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.Os
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.Sh NAME
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.Nm arch
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.Nd Architecture-specific details
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.Sh DESCRIPTION
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Differences between CPU architectures and platforms supported by
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.Fx .
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.Ss Introduction
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This document is a quick reference of key ABI details of
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.Fx
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architecture ports.
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For full details consult the processor-specific ABI supplement
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documentation.
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.Pp
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If not explicitly mentioned, sizes are in bytes.
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The architecture details in this document apply to
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.Fx 11.0
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and later, unless otherwise noted.
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.Pp
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.Fx
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uses a flat address space.
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Variables of types
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.Vt unsigned long ,
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.Vt uintptr_t ,
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and
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.Vt size_t
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and pointers all have the same representation.
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.Pp
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In order to maximize compatibility with future pointer integrity mechanisms,
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manipulations of pointers as integers should be performed via
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.Vt uintptr_t
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or
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.Vt intptr_t
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and no other types.
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In particular,
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.Vt long
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and
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.Vt ptrdiff_t
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should be avoided.
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.Pp
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On some architectures, e.g.,
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.Dv sparc64 ,
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.Dv powerpc
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and AIM variants of
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.Dv powerpc64 ,
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the kernel uses a separate address space.
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On other architectures, kernel and a user mode process share a
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single address space.
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The kernel is located at the highest addresses.
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.Pp
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On each architecture, the main user mode thread's stack starts near
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the highest user address and grows down.
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.Pp
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.Fx
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architecture support varies by release.
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This table shows the first
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.Fx
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release to support each architecture, and, for discontinued
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architectures, the final release.
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.Pp
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.Bl -column -offset indent "Sy Architecture" "Sy Initial Release" "Sy Final Release"
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.It Sy Architecture Ta Sy Initial Release Ta Sy Final Release
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.It aarch64 Ta 11.0
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.It alpha Ta 3.2 Ta 6.4
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.It amd64 Ta 5.1
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.It arm Ta 6.0 Ta 12.x
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.It armeb Ta 8.0 Ta 11.x
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.It armv6 Ta 10.0
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.It armv7 Ta 12.0
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.It ia64 Ta 5.0 Ta 10.4
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.It i386 Ta 1.0
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.It mips Ta 8.0
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.It mipsel Ta 9.0
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.It mipselhf Ta 12.0
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.It mipshf Ta 12.0
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.It mipsn32 Ta 9.0
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.It mips64 Ta 9.0
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.It mips64el Ta 9.0
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.It mips64elhf Ta 12.0
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.It mips64hf Ta 12.0
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.It pc98 Ta 2.2 Ta 11.x
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.It powerpc Ta 6.0
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.It powerpcspe Ta 12.0
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.It powerpc64 Ta 6.0
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.It riscv64 Ta 12.0
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.It riscv64sf Ta 12.0
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.It sparc64 Ta 5.0 Ta 12.x
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.El
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.Ss Type sizes
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All
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.Fx
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architectures use some variant of the ELF (see
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.Xr elf 5 )
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.Sy Application Binary Interface
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(ABI) for the machine processor.
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All supported ABIs can be divided into two groups:
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.Bl -tag -width "Dv ILP32"
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.It Dv ILP32
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.Vt int ,
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.Vt long ,
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.Vt void *
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types machine representations all have 4-byte size.
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.It Dv LP64
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.Vt int
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type machine representation uses 4 bytes,
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while
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.Vt long
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and
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.Vt void *
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are 8 bytes.
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.El
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Compilers define the
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.Dv _LP64
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symbol when compiling for an
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.Dv LP64
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ABI.
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.Pp
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Some machines support more than one
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.Fx
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ABI.
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Typically these are 64-bit machines, where the
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.Dq native
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.Dv LP64
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execution environment is accompanied by the
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.Dq legacy
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.Dv ILP32
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environment, which was the historical 32-bit predecessor for 64-bit evolution.
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Examples are:
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.Bl -column -offset indent "Dv powerpc64" "Sy ILP32 counterpart"
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.It Sy LP64 Ta Sy ILP32 counterpart
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.It Dv amd64 Ta Dv i386
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.It Dv powerpc64 Ta Dv powerpc
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.It Dv mips64* Ta Dv mips*
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.It Dv aarch64 Ta Dv armv6/armv7
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.El
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.Dv aarch64
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will support execution of
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.Dv armv6
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or
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.Dv armv7
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binaries if the CPU implements
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.Dv AArch32
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execution state, however
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.Dv armv5
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binaries aren't supported.
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.Pp
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On all supported architectures:
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.Bl -column -offset -indent "long long" "Size"
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.It Sy Type Ta Sy Size
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.It short Ta 2
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.It int Ta 4
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.It long Ta sizeof(void*)
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.It long long Ta 8
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.It float Ta 4
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.It double Ta 8
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.El
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Integers are represented in two's complement.
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Alignment of integer and pointer types is natural, that is,
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the address of the variable must be congruent to zero modulo the type size.
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Most ILP32 ABIs, except
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.Dv arm ,
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require only 4-byte alignment for 64-bit integers.
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.Pp
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Machine-dependent type sizes:
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.Bl -column -offset indent "Sy Architecture" "Sy void *" "Sy long double" "Sy time_t"
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.It Sy Architecture Ta Sy void * Ta Sy long double Ta Sy time_t
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.It aarch64 Ta 8 Ta 16 Ta 8
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.It amd64 Ta 8 Ta 16 Ta 8
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.It arm Ta 4 Ta 8 Ta 8
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.It armv6 Ta 4 Ta 8 Ta 8
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.It i386 Ta 4 Ta 12 Ta 4
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.It mips Ta 4 Ta 8 Ta 8
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.It mipsel Ta 4 Ta 8 Ta 8
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.It mipselhf Ta 4 Ta 8 Ta 8
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.It mipshf Ta 4 Ta 8 Ta 8
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.It mipsn32 Ta 4 Ta 8 Ta 8
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.It mips64 Ta 8 Ta 8 Ta 8
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.It mips64el Ta 8 Ta 8 Ta 8
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.It mips64elhf Ta 8 Ta 8 Ta 8
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.It mips64hf Ta 8 Ta 8 Ta 8
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.It powerpc Ta 4 Ta 8 Ta 8
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.It powerpcspe Ta 4 Ta 8 Ta 8
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.It powerpc64 Ta 8 Ta 8 Ta 8
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.It riscv64 Ta 8 Ta 16 Ta 8
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.It riscv64sf Ta 8 Ta 16 Ta 8
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.It sparc64 Ta 8 Ta 16 Ta 8
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.El
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.Pp
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.Sy time_t
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is 8 bytes on all supported architectures except i386.
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.Ss Endianness and Char Signedness
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.Bl -column -offset indent "Sy Architecture" "Sy Endianness" "Sy char Signedness"
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.It Sy Architecture Ta Sy Endianness Ta Sy char Signedness
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.It aarch64 Ta little Ta unsigned
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.It amd64 Ta little Ta signed
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.It arm Ta little Ta unsigned
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.It armv6 Ta little Ta unsigned
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.It armv7 Ta little Ta unsigned
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.It i386 Ta little Ta signed
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.It mips Ta big Ta signed
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.It mipsel Ta little Ta signed
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.It mipselhf Ta little Ta signed
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.It mipshf Ta big Ta signed
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.It mipsn32 Ta big Ta signed
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.It mips64 Ta big Ta signed
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.It mips64el Ta little Ta signed
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.It mips64elhf Ta little Ta signed
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.It mips64hf Ta big Ta signed
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.It powerpc Ta big Ta unsigned
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.It powerpcspe Ta big Ta unsigned
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.It powerpc64 Ta big Ta unsigned
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.It riscv64 Ta little Ta signed
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.It riscv64sf Ta little Ta signed
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.It sparc64 Ta big Ta signed
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.El
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.Ss Page Size
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.Bl -column -offset indent "Sy Architecture" "Sy Page Sizes"
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.It Sy Architecture Ta Sy Page Sizes
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.It aarch64 Ta 4K, 2M, 1G
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.It amd64 Ta 4K, 2M, 1G
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.It arm Ta 4K
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.It armv6 Ta 4K, 1M
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.It armv7 Ta 4K, 1M
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.It i386 Ta 4K, 2M (PAE), 4M
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.It mips Ta 4K
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.It mipsel Ta 4K
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.It mipselhf Ta 4K
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.It mipshf Ta 4K
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.It mipsn32 Ta 4K
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.It mips64 Ta 4K
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.It mips64el Ta 4K
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.It mips64elhf Ta 4K
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.It mips64hf Ta 4K
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.It powerpc Ta 4K
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.It powerpcspe Ta 4K
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.It powerpc64 Ta 4K
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.It riscv64 Ta 4K
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.It riscv64sf Ta 4K
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.It sparc64 Ta 8K
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.El
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.Ss Floating Point
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.Bl -column -offset indent "Sy Architecture" "Sy float, double" "Sy long double"
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.It Sy Architecture Ta Sy float, double Ta Sy long double
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.It aarch64 Ta hard Ta soft, quad precision
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.It amd64 Ta hard Ta hard, 80 bit
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.It arm Ta soft Ta soft, double precision
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.It armv6 Ta hard Ta hard, double precision
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.It armv7 Ta hard Ta hard, double precision
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.It i386 Ta hard Ta hard, 80 bit
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.It mips Ta soft Ta identical to double
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.It mipsel Ta soft Ta identical to double
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.It mipselhf Ta hard Ta identical to double
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.It mipshf Ta hard Ta identical to double
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.It mipsn32 Ta soft Ta identical to double
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.It mips64 Ta soft Ta identical to double
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.It mips64el Ta soft Ta identical to double
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.It mips64elhf Ta hard Ta identical to double
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.It mips64hf Ta hard Ta identical to double
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.It powerpc Ta hard Ta hard, double precision
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.It powerpcspe Ta hard Ta hard, double precision
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.It powerpc64 Ta hard Ta hard, double precision
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.It riscv64 Ta hard Ta hard, double precision
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.It riscv64sf Ta soft Ta soft, double precision
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.It sparc64 Ta hard Ta hard, quad precision
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.El
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.Ss Default Tool Chain
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.Fx uses a variety of tool chain components for the supported CPU
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architectures:
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.Xr clang 1
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and
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.Xr ld.lld 1
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provided by the base system,
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GNU
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.Xr gcc 1
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and Binutils
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.Xr ld 1 ,
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or an external toolchain compiler and linker provided by a port or package.
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This table shows the default tool chain for each architecture.
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.Bl -column -offset indent "Sy Architecture" "Sy Compiler" "Sy Linker"
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.It Sy Architecture Ta Sy Compiler Ta Sy Linker
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.It aarch64 Ta Clang Ta lld
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.It amd64 Ta Clang Ta lld
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.It arm Ta Clang Ta GNU ld 2.17.50
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.It armv6 Ta Clang Ta lld
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.It armv7 Ta Clang Ta lld
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.It i386 Ta Clang Ta lld
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.It mips Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mipsel Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mipselhf Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mipshf Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mipsn32 Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mips64 Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mips64el Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mips64elhf Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It mips64hf Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It powerpc Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It powerpcspe Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It powerpc64 Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.It riscv64 Ta GCC(1) Ta GNU ld(1)
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.It riscv64sf Ta GCC(1) Ta GNU ld(1)
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.It sparc64 Ta GCC 4.2.1 Ta GNU ld 2.17.50
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.El
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.Pp
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(1) External toolchain provided by ports/packages.
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.Pp
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Note that GCC 4.2.1 is deprecated, and scheduled for removal on 2020-03-31.
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Any CPU architectures not migrated by then
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(to either base system Clang or external toolchain)
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may be removed from the tree after that date.
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Unless the make variable
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.Dv MAKE_OBSOLETE_GCC
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is defined, make universe will not build mips, powerpc, nor sparc64
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architectures unless the xtoolchain binaries have been installed for
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the architecture.
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.Ss MACHINE_ARCH vs MACHINE_CPUARCH vs MACHINE
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.Dv MACHINE_CPUARCH
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should be preferred in Makefiles when the generic
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architecture is being tested.
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.Dv MACHINE_ARCH
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should be preferred when there is something specific to a particular type of
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architecture where there is a choice of many, or could be a choice of many.
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Use
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.Dv MACHINE
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when referring to the kernel, interfaces dependent on a specific type of kernel
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or similar things like boot sequences.
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.Bl -column -offset indent "Dv MACHINE" "Dv MACHINE_CPUARCH" "Dv MACHINE_ARCH"
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.It Dv MACHINE Ta Dv MACHINE_CPUARCH Ta Dv MACHINE_ARCH
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.It arm64 Ta aarch64 Ta aarch64
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.It amd64 Ta amd64 Ta amd64
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.It arm Ta arm Ta arm, armv6, armv7
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.It i386 Ta i386 Ta i386
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.It mips Ta mips Ta mips, mipsel, mips64, mips64el, mipshf, mipselhf, mips64elhf, mipsn32
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.It powerpc Ta powerpc Ta powerpc, powerpcspe, powerpc64
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.It riscv Ta riscv Ta riscv64, riscv64sf
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.It sparc64 Ta sparc64 Ta sparc64
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.El
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.Ss Predefined Macros
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The compiler provides a number of predefined macros.
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Some of these provide architecture-specific details and are explained below.
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Other macros, including those required by the language standard, are not
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included here.
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.Pp
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The full set of predefined macros can be obtained with this command:
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.Bd -literal -offset indent
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cc -x c -dM -E /dev/null
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.Ed
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.Pp
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Common type size and endianness macros:
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.Bl -column -offset indent "BYTE_ORDER" "Sy Meaning"
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.It Sy Macro Ta Sy Meaning
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.It Dv __LP64__ Ta 64-bit (8-byte) long and pointer, 32-bit (4-byte) int
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.It Dv __ILP32__ Ta 32-bit (4-byte) int, long and pointer
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.It Dv BYTE_ORDER Ta Either Dv BIG_ENDIAN or Dv LITTLE_ENDIAN .
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.Dv PDP11_ENDIAN
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is not used on
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.Fx .
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.El
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.Pp
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Architecture-specific macros:
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.Bl -column -offset indent "Sy Architecture" "Sy Predefined macros"
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.It Sy Architecture Ta Sy Predefined macros
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.It aarch64 Ta Dv __aarch64__
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.It amd64 Ta Dv __amd64__, Dv __x86_64__
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.It arm Ta Dv __arm__
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.It armv6 Ta Dv __arm__, Dv __ARM_ARCH >= 6
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.It armv7 Ta Dv __arm__, Dv __ARM_ARCH >= 7
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.It i386 Ta Dv __i386__
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.It mips Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
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.It mipsel Ta Dv __mips__, Dv __mips_o32
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.It mipselhf Ta Dv __mips__, Dv __mips_o32
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.It mipshf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_o32
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.It mipsn32 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n32
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.It mips64 Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
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.It mips64el Ta Dv __mips__, Dv __mips_n64
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.It mips64elhf Ta Dv __mips__, Dv __mips_n64
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.It mips64hf Ta Dv __mips__, Dv __MIPSEB__, Dv __mips_n64
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.It powerpc Ta Dv __powerpc__
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.It powerpcspe Ta Dv __powerpc__, Dv __SPE__
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.It powerpc64 Ta Dv __powerpc__, Dv __powerpc64__
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.It riscv64 Ta Dv __riscv, Dv __riscv_xlen == 64
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.It riscv64sf Ta Dv __riscv, Dv __riscv_xlen == 64
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.It sparc64 Ta Dv __sparc64__
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.El
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.Pp
|
|
Compilers may define additional variants of architecture-specific macros.
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The macros above are preferred for use in
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.Fx .
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.Ss Important Xr make 1 variables
|
|
Most of the externally settable variables are defined in the
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.Xr build 7
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|
man page.
|
|
These variables are not otherwise documented and are used extensively
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in the build system.
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.Bl -column -offset indent "Sy Variable" "Sy Meaning and usage"
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.It Dv MACHINE Represent the hardware platform.
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This is the same as the native platform's
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.Xr uname 1
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.Fl m
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output.
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|
It defines both the userland / kernel interface, as well as the
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bootloader / kernel interface.
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|
It should only be used in these contexts.
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|
Each CPU architecture may have multiple hardware platforms it supports
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where
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.Dv MACHINE
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differs among them.
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|
It is used to collect together all the files from
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.Xr config 8
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to build the kernel.
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It is often the same as
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.Dv MACHINE_ARCH
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just as one CPU architecture can be implemented by many different
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hardware platforms, one hardware platform may support multiple CPU
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architecture family members, though with different binaries.
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For example,
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.Dv MACHINE
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of i386 supported the IBM-AT hardware platform while the
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.Dv MACHINE
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of pc98 supported the Japanese company NEC's PC-9801 and PC-9821
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hardware platforms.
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|
Both of these hardware platforms supported only the
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.Dv MACHINE_ARCH
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|
of i386 where they shared a common ABI, except for certain kernel /
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userland interfaces relating to underlying hardware platform
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|
differences in bus architecture, device enumeration and boot interface.
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|
Generally,
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.Dv MACHINE
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should only be used in src/sys and src/stand or in system imagers or
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installers.
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.It Dv MACHINE_ARCH Represents the CPU processor architecture.
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|
This is the same as the native platforms
|
|
.Xr uname 1
|
|
.Fl p
|
|
output.
|
|
It defines the CPU instruction family supported.
|
|
It may also encode a variation in the byte ordering of multi-byte
|
|
integers (endian).
|
|
It may also encode a variation in the size of the integer or pointer.
|
|
It may also encode a ISA revision.
|
|
It may also encode hard versus soft floating point ABI and usage.
|
|
It may also encode a variant ABI when the other factors do not
|
|
uniquely define the ABI (e.g., MIPS' n32 ABI).
|
|
It, along with
|
|
.Dv MACHINE ,
|
|
defines the ABI used by the system.
|
|
For example, the MIPS CPU processor family supports 9 different
|
|
combinations encoding pointer size, endian and hard versus soft float (for
|
|
8 combinations) as well as N32 (which only ever had one variation of
|
|
all these).
|
|
Generally, the plain CPU name specifies the most common (or at least
|
|
first) variant of the CPU.
|
|
This is why mips and mips64 imply 'big endian' while 'arm' and 'armv7'
|
|
imply little endian.
|
|
If we ever were to support the so-called x32 ABI (using 32-bit
|
|
pointers on the amd64 architecture), it would most likely be encoded
|
|
as amd64-x32.
|
|
It is unfortunate that amd64 specifies the 64-bit evolution of the x86
|
|
platform (it matches the 'first rule') as everybody else uses x86_64.
|
|
There is no standard name for the processor: each OS selects its own
|
|
conventions.
|
|
.It Dv MACHINE_CPUARCH Represents the source location for a given
|
|
.Dv MACHINE_ARCH .
|
|
It is generally the common prefix for all the MACHINE_ARCH that
|
|
share the same implementation, though 'riscv' breaks this rule.
|
|
For example,
|
|
.Dv MACHINE_CPUARCH
|
|
is defined to be mips for all the flavors of mips that we support
|
|
since we support them all with a shared set of sources.
|
|
While amd64 and i386 are closely related, MACHINE_CPUARCH is not x86
|
|
for them.
|
|
The FreeBSD source base supports amd64 and i386 with two
|
|
distinct source bases living in subdirectories named amd64 and i386
|
|
(though behind the scenes there's some sharing that fits into this
|
|
framework).
|
|
.It Dv CPUTYPE Sets the flavor of
|
|
.Dv MACHINE_ARCH
|
|
to build.
|
|
It is used to optimize the build for a specific CPU / core that the
|
|
binaries run on.
|
|
Generally, this does not change the ABI, though it can be a fine line
|
|
between optimization for specific cases.
|
|
.It Dv TARGET Used to set
|
|
.Dv MACHINE
|
|
in the top level Makefile for cross building.
|
|
Unused outside of that scope.
|
|
It is not passed down to the rest of the build.
|
|
Makefiles outside of the top level should not use it at all (though
|
|
some have their own private copy for hysterical raisons).
|
|
.It Dv TARGET_ARCH Used to set
|
|
.Dv MACHINE_ARCH
|
|
by the top level Makefile for cross building.
|
|
Like
|
|
.Dv TARGET , it is unused outside of that scope.
|
|
.El
|
|
.Sh SEE ALSO
|
|
.Xr src.conf 5 ,
|
|
.Xr build 7
|
|
.Sh HISTORY
|
|
An
|
|
.Nm
|
|
manual page appeared in
|
|
.Fx 11.1 .
|