f570e9e145
221804, 221805, 222004, 222006, 222055, 222820, 1135077, 1135118, 1136259 Add atse(4), a driver for the Altera Triple Speed Ethernet MegaCore. The current driver support gigabit Ethernet speeds only and works with the MegaCore only in the internal FIFO configuration in the soon to be open sourced BERI CPU configuration. Submitted by: bz MFC after: 3 days Sponsored by: DARPA/AFRL
487 lines
19 KiB
C
487 lines
19 KiB
C
/*-
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* Copyright (c) 2012 Bjoern A. Zeeb
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-11-C-0249)
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* ("MRC2"), as part of the DARPA MRC research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_IF_ATSEREG_H
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#define _DEV_IF_ATSEREG_H
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#define ATSE_VENDOR 0x6af7
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#define ATSE_DEVICE 0x00bd
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/* See hints file/fdt for ctrl port and Avalon FIFO addresses. */
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/* Section 3. Parameter Settings. */
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/*
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* This is a lot of options that affect the way things are synthesized.
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* We cannot really make them all hints and most of them might be stale.
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*/
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/* 3-1 Core Configuration */
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#if 0
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static const char *atse_core_core_variation[] = {
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[0] = "10/100/1000 Mbps Ethernet MAC only",
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[1] = "10/100/1000 Mbps Ethernet MAC with 1000BASE-X/SGMII PCS",
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[2] = "1000BASE-X/SGMII PCS only",
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[3] = "1000 Mbps Small MAC",
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[4] = "10/100 Mbps Small MAC",
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NULL
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};
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static const char *atse_core_interface[] = {
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[0] = "MII", /* Core variation 4. */
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[1] = "GMII", /* Core variation 3. */
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[2] = "RGMII", /* Core variation 0,1,3. */
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[3] = "MII/GMII", /* Core variation 0,1. */
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NULL
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};
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#endif
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#define CORE_CORE_VARIATION 1 /* atse_core_core_variation[] */
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#define CORE_INTERFACE 3 /* atse_core_interface[] */
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#define CORE_USE_INTERNAL_FIFO 1
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#define CORE_NUMBER_OF_PORTS 1 /* Internal FIFO count. */
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#define CORE_USE_TRANSCEIVER_BLOCK 1 /* SGMII PCS transceiver:
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* LVDS I/O. */
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/* 3-2 MAC Options. */
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/* Ethernet MAC Options. */
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#define MAC_ENABLE_10_100_HDX_SUPPORT 0
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#define MAC_ENABLE_RG_G_MII_LOOPBACK 0
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#define MAC_ENABLE_SUPL_MAC_UCAST_ADDR 0 /* Supplementary MAC unicast. */
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#define MAC_INCLUDE_STATISTICS_COUNTERS 0
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#define MAC_STATISTICS_COUNTERS_64BIT 0
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#define MAC_INCLUDE_MC_HASHTABLE 0 /* Multicast. */
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#define MAC_ALIGN_PKTHDR_32BIT 1
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#define MAC_ENABLE_FDX_FLOW_CTRL 0
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#define MAC_ENABLE_VLAN_DETECTION 0 /* VLAN and stacked VLANs. */
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#define MAC_ENABLE_MAGIC_PKT_DETECTION 0
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/* MDIO Module. */
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#define MAC_MDIO_INCLUDE_MDIO_MODULE 1
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#define MAC_MDIO_HOST_CLOCK_DIVISOR 40 /* Not just On/Off. */
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/* 3-4 FIFO Options. */
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/* Width and Memory Type. */
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#if 0
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static char *fifo_memory_block[] = {
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[0] = "M4K",
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[1] = "M9K",
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[2] = "M144K",
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[3] = "MRAM",
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[4] = "AUTO",
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NULL
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};
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#endif
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#define FIFO_MEMORY_BLOCK 4
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#define FIFO_WITDH 32 /* Other: 8 bits. */
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/* Depth. */
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#define FIFO_DEPTH_TX 2048 /* 64 .. 64k, 2048x32bits. */
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#define FIFO_DEPTH_RX 2048 /* 64 .. 64k, 2048x32bits. */
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#define ATSE_TX_LIST_CNT 5 /* Certainly not bufferbloat. */
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/* 3-4 PCS/Transceiver Options */
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/* PCS Options. */
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#define PCS_TXRX_PHY_ID 0x00000000 /* 32 bits */
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#define PCS_TXRX_ENABLE_SGMII_BRIDGE 0
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/* Transceiver Options. */
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#define PCS_TXRX_EXP_POWER_DOWN_SIGNAL 0 /* Export power down signal. */
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#define PCS_TXRX_ENABLE_DYNAMIC_RECONF 0 /* Dynamic trans. reconfig. */
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#define PCS_TXRX_STARTING_CHANNEL 0 /* 0..284. */
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/* -------------------------------------------------------------------------- */
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/* XXX more values based on the bitmaps provided. Cleanup. */
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/* See regs above. */
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#define AVALON_FIFO_TX_BLOCK_DIAGRAM 0
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#define AVALON_FIFO_TX_BLOCK_DIAGRAM_SHOW_SIGANLS 0
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#define AVALON_FIFO_TX_PARAM_SINGLE_RESET_MODE 0
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#define AVALON_FIFO_TX_BASIC_OPTS_DEPTH 16
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#define AVALON_FIFO_TX_BASIC_OPTS_ALLOW_BACKPRESSURE 1
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#define AVALON_FIFO_TX_BASIC_OPTS_CLOCK_SETTING "Single Clock Mode"
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#define AVALON_FIFO_TX_BASIC_OPTS_FIFO_IMPL "Construct FIFO from embedded memory blocks"
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#define AVALON_FIFO_TX_STATUS_PORT_CREATE_STATUS_INT_FOR_INPUT 1
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#define AVALON_FIFO_TX_STATUS_PORT_CREATE_STATUS_INT_FOR_OUTPUT 0
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#define AVALON_FIFO_TX_STATUS_PORT_ENABLE_IRQ_FOR_STATUS_PORT 1
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#define AVALON_FIFO_TX_INPUT_TYPE "AVALONMM_WRITE"
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#define AVALON_FIFO_TX_OUTPUT_TYPE "AVALONST_SOURCE"
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#define AVALON_FIFO_TX_AVALON_MM_PORT_SETTINGS_DATA_WIDTH ""
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#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_BITS_PER_SYMBOL 8
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#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_SYM_PER_BEAT 4
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#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_ERROR_WIDTH 1
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#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_CHANNEL_WIDTH 0
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#define AVALON_FIFO_TX_AVALON_ST_PORT_SETTINGS_ENABLE_PACKET_DATA 1
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#define AVALON_FIFO_RX_BLOCK_DIAGRAM 0
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#define AVALON_FIFO_RX_BLOCK_DIAGRAM_SHOW_SIGNALS 0
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#define AVALON_FIFO_RX_PARAM_SINGLE_RESET_MODE 0
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#define AVALON_FIFO_RX_BASIC_OPTS_DEPTH 16
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#define AVALON_FIFO_RX_BASIC_OPTS_ALLOW_BACKPRESSURE 1
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#define AVALON_FIFO_RX_BASIC_OPTS_CLOCK_SETTING "Single Clock Mode"
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#define AVALON_FIFO_RX_BASIC_OPTS_FIFO_IMPL "Construct FIFO from embedded memory blocks"
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#define AVALON_FIFO_RX_STATUS_PORT_CREATE_STATUS_INT_FOR_INPUT 1
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#define AVALON_FIFO_RX_STATUS_PORT_CREATE_STATUS_INT_FOR_OUTPUT 0
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#define AVALON_FIFO_RX_STATUS_PORT_ENABLE_IRQ_FOR_STATUS_PORT 1
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#define AVALON_FIFO_RX_INPUT_TYPE "AVALONST_SINK"
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#define AVALON_FIFO_RX_OUTPUT_TYPE "AVALONMM_READ"
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#define AVALON_FIFO_RX_AVALON_MM_PORT_SETTINGS_DATA_WIDTH ""
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#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_BITS_PER_SYMBOL 8
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#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_SYM_PER_BEAT 4
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#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_ERROR_WIDTH 6
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#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_CHANNEL_WIDTH 0
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#define AVALON_FIFO_RX_AVALON_ST_PORT_SETTINGS_ENABLE_PACKET_DATA 1
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/* -------------------------------------------------------------------------- */
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/* 5. Configuration Register Space. */
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/* 5-1, MAC Configuration Register Space; Dword offsets. */
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/* 0x00 - 0x17, Base Configuration. */
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#define BASE_CONFIG_REV 0x00 /* ro, IP Core ver. */
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#define BASE_CFG_REV_VER_MASK 0x0000FFFF
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#define BASE_CFG_REV_CUST_VERSION__MASK 0xFFFF0000
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#define BASE_CFG_SCRATCH 0x01 /* rw, 0 */
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#define BASE_CFG_COMMAND_CONFIG 0x02 /* rw, 0 */
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#define BASE_CFG_COMMAND_CONFIG_TX_ENA (1<<0) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_RX_ENA (1<<1) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_XON_GEN (1<<2) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_ETH_SPEED (1<<3) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_PROMIS_EN (1<<4) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_PAD_EN (1<<5) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_CRC_FWD (1<<6) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_PAUSE_FWD (1<<7) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_PAUSE_IGNORE (1<<8) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_TX_ADDR_INS (1<<9) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_HD_ENA (1<<10) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_EXCESS_COL (1<<11) /* ro */
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#define BASE_CFG_COMMAND_CONFIG_LATE_COL (1<<12) /* ro */
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#define BASE_CFG_COMMAND_CONFIG_SW_RESET (1<<13) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_MHASH_SEL (1<<14) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_LOOP_ENA (1<<15) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_TX_ADDR_SEL (1<<16|1<<17|1<<18) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_MAGIC_ENA (1<<19) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_SLEEP (1<<20) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_WAKEUP (1<<21) /* ro */
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#define BASE_CFG_COMMAND_CONFIG_XOFF_GEN (1<<22) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_CNTL_FRM_ENA (1<<23) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_NO_LGTH_CHECK (1<<24) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_ENA_10 (1<<25) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_RX_ERR_DISC (1<<26) /* rw */
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#define BASE_CFG_COMMAND_CONFIG_DISABLE_READ_TIMEOUT (1<<27) /* rw */
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/* 28-30 Reserved. */ /* - */
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#define BASE_CFG_COMMAND_CONFIG_CNT_RESET (1<<31) /* rw */
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#define BASE_CFG_MAC_0 0x03 /* rw, 0 */
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#define BASE_CFG_MAC_1 0x04 /* rw, 0 */
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#define BASE_CFG_FRM_LENGTH 0x05 /* rw/ro, 1518 */
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#define BASE_CFG_PAUSE_QUANT 0x06 /* rw, 0 */
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#define BASE_CFG_RX_SECTION_EMPTY 0x07 /* rw/ro, 0 */
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#define BASE_CFG_RX_SECTION_FULL 0x08 /* rw/ro, 0 */
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#define BASE_CFG_TX_SECTION_EMPTY 0x09 /* rw/ro, 0 */
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#define BASE_CFG_TX_SECTION_FULL 0x0A /* rw/ro, 0 */
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#define BASE_CFG_RX_ALMOST_EMPTY 0x0B /* rw/ro, 0 */
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#define BASE_CFG_RX_ALMOST_FULL 0x0C /* rw/ro, 0 */
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#define BASE_CFG_TX_ALMOST_EMPTY 0x0D /* rw/ro, 0 */
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#define BASE_CFG_TX_ALMOST_FULL 0x0E /* rw/ro, 0 */
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#define BASE_CFG_MDIO_ADDR0 0x0F /* rw, 0 */
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#define BASE_CFG_MDIO_ADDR1 0x10 /* rw, 1 */
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#define BASE_CFG_HOLDOFF_QUANT 0x11 /* rw, 0xFFFF */
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/* 0x12-0x16 Reserved. */ /* -, 0 */
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#define BASE_CFG_TX_IPG_LENGTH 0x17 /* rw, 0 */
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/* 0x18 - 0x38, Statistics Counters. */
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#define STATS_A_MAC_ID_0 0x18 /* ro */
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#define STATS_A_MAC_ID_1 0x19 /* ro */
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#define STATS_A_FRAMES_TX_OK 0x1A /* ro */
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#define STATS_A_FRAMES_RX_OK 0x1B /* ro */
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#define STATS_A_FCS_ERRORS 0x1C /* ro */
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#define STATS_A_ALIGNMENT_ERRORS 0x1D /* ro */
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#define STATS_A_OCTETS_TX_OK 0x1E /* ro */
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#define STATS_A_OCTETS_RX_OK 0x1F /* ro */
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#define STATS_A_TX_PAUSE_MAX_CTRL_FRAME 0x20 /* ro */
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#define STATS_A_RX_PAUSE_MAX_CTRL_FRAME 0x21 /* ro */
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#define STATS_IF_IN_ERRORS 0x22 /* ro */
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#define STATS_IF_OUT_ERRORS 0x23 /* ro */
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#define STATS_IF_IN_UCAST_PKTS 0x24 /* ro */
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#define STATS_IF_IN_MULTICAST_PKTS 0x25 /* ro */
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#define STATS_IF_IN_BROADCAST_PKTS 0x26 /* ro */
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#define STATS_IF_OUT_DISCARDS 0x27 /* ro */
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#define STATS_IF_OUT_UCAST_PKTS 0x28 /* ro */
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#define STATS_IF_OUT_MULTICAST_PKTS 0x29 /* ro */
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#define STATS_IF_OUT_BROADCAST_PKTS 0x2A /* ro */
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#define STATS_ETHER_STATS_DROP_EVENT 0x2B /* ro */
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#define STATS_ETHER_STATS_OCTETS 0x2C /* ro */
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#define STATS_ETHER_STATS_PKTS 0x2D /* ro */
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#define STATS_ETHER_STATS_USIZE_PKTS 0x2E /* ro */
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#define STATS_ETHER_STATS_OSIZE_PKTS 0x2F /* ro */
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#define STATS_ETHER_STATS_PKTS_64_OCTETS 0x30 /* ro */
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#define STATS_ETHER_STATS_PKTS_65_TO_127_OCTETS 0x31 /* ro */
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#define STATS_ETHER_STATS_PKTS_128_TO_255_OCTETS 0x32 /* ro */
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#define STATS_ETHER_STATS_PKTS_256_TO_511_OCTETS 0x33 /* ro */
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#define STATS_ETHER_STATS_PKTS_512_TO_1023_OCTETS 0x34 /* ro */
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#define STATS_ETHER_STATS_PKTS_1024_TO_1518_OCTETS 0x35 /* ro */
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#define STATS_ETHER_STATS_PKTS_1519_TO_X_OCTETS 0x36 /* ro */
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#define STATS_ETHER_STATS_JABBERS 0x37 /* ro */
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#define STATS_ETHER_STATS_FRAGMENTS 0x38 /* ro */
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/* 0x39, Reserved. */ /* - */
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/* 0x3A, Transmit Command. */
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#define TX_CMD_STAT 0x3A /* rw */
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#define TX_CMD_STAT_OMIT_CRC (1<<17)
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#define TX_CMD_STAT_TX_SHIFT16 (1<<18)
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/* 0x3B, Receive Command. */
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#define RX_CMD_STAT 0x3B /* rw */
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#define RX_CMD_STAT_RX_SHIFT16 (1<<25)
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/* 0x3C - 0x3E, Extended Statistics Counters. */
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#define ESTATS_MSB_A_OCTETS_TX_OK 0x3C /* ro */
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#define ESTATS_MSB_A_OCTETS_RX_OK 0x3D /* ro */
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#define ESTATS_MSB_ETHER_STATS_OCTETS 0x3E /* ro */
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/* 0x3F, Reserved. */
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/* 0x40 - 0x7F, Multicast Hash Table. */
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#define MHASH_START 0x40
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#define MHASH_LEN 0x3F
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/* 0x80 - 0x9F, MDIO Space 0 or PCS Function Configuration. */
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#define MDIO_0_START 0x80
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/* The following are offsets to the first PCS register at 0x80. */
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/* See sys/dev/mii/mii.h. */
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#define PCS_CONTROL 0x00 /* rw */
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/* Bits 0:4, Reserved. */ /* - */
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#define PCS_CONTROL_UNIDIRECTIONAL_ENABLE (1<<5) /* rw */
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#define PCS_CONTROL_SPEED_SELECTION (1<<6|1<<13) /* ro */
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#define PCS_CONTROL_COLLISION_TEST (1<<7) /* ro */
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#define PCS_CONTROL_DUPLEX_MODE (1<<8) /* ro */
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#define PCS_CONTROL_RESTART_AUTO_NEGOTIATION (1<<9) /* rw */
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#define PCS_CONTROL_ISOLATE (1<<10) /* rw */
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#define PCS_CONTROL_POWERDOWN (1<<11) /* rw */
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#define PCS_CONTROL_AUTO_NEGOTIATION_ENABLE (1<<12) /* rw */
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/* See bit 6 above. */ /* ro */
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#define PCS_CONTROL_LOOPBACK (1<<14) /* rw */
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#define PCS_CONTROL_RESET (1<<15) /* rw */
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#define PCS_STATUS 0x01 /* ro */
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#define PCS_STATUS_EXTENDED_CAPABILITY (1<<0) /* ro */
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#define PCS_STATUS_JABBER_DETECT (1<<1) /* -, 0 */
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#define PCS_STATUS_LINK_STATUS (1<<2) /* ro */
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#define PCS_STATUS_AUTO_NEGOTIATION_ABILITY (1<<3) /* ro */
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#define PCS_STATUS_REMOTE_FAULT (1<<4) /* -, 0 */
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#define PCS_STATUS_AUTO_NEGOTIATION_COMPLETE (1<<5) /* ro */
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#define PCS_STATUS_MF_PREAMBLE_SUPPRESSION (1<<6) /* -, 0 */
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#define PCS_STATUS_UNIDIRECTIONAL_ABILITY (1<<7) /* ro */
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#define PCS_STATUS_EXTENDED_STATUS (1<<8) /* -, 0 */
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#define PCS_STATUS_100BASET2_HALF_DUPLEX (1<<9) /* ro */
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#define PCS_STATUS_100BASET2_FULL_DUPLEX (1<<10) /* ro */
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#define PCS_STATUS_10MBPS_HALF_DUPLEX (1<<11) /* ro */
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#define PCS_STATUS_10MBPS_FULL_DUPLEX (1<<12) /* ro */
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#define PCS_STATUS_100BASE_X_HALF_DUPLEX (1<<13) /* ro */
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#define PCS_STATUS_100BASE_X_FULL_DUPLEX (1<<14) /* ro */
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#define PCS_STATUS_100BASE_T4 (1<<15) /* ro */
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#define PCS_PHY_IDENTIFIER_0 0x02 /* ro */
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#define PCS_PHY_IDENTIFIER_1 0x03 /* ro */
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#define PCS_DEV_ABILITY 0x04 /* rw */
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/* 1000BASE-X */
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/* Bits 0:4, Reserved. */ /* - */
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#define PCS_DEV_ABILITY_1000BASE_X_FD (1<<5) /* rw */
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#define PCS_DEV_ABILITY_1000BASE_X_HD (1<<6) /* rw */
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#define PCS_DEV_ABILITY_1000BASE_X_PS1 (1<<7) /* rw */
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#define PCS_DEV_ABILITY_1000BASE_X_PS2 (1<<8) /* rw */
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/* Bits 9:11, Reserved. */ /* - */
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#define PCS_DEV_ABILITY_1000BASE_X_RF1 (1<<12) /* rw */
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#define PCS_DEV_ABILITY_1000BASE_X_RF2 (1<<13) /* rw */
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#define PCS_DEV_ABILITY_1000BASE_X_ACK (1<<14) /* rw */
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#define PCS_DEV_ABILITY_1000BASE_X_NP (1<<15) /* rw */
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#define PCS_PARTNER_ABILITY 0x05 /* ro */
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/* 1000BASE-X */
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/* Bits 0:4, Reserved. */ /* - */
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#define PCS_PARTNER_ABILITY_1000BASE_X_FD (1<<5) /* ro */
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#define PCS_PARTNER_ABILITY_1000BASE_X_HD (1<<6) /* ro */
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#define PCS_PARTNER_ABILITY_1000BASE_X_PS1 (1<<7) /* ro */
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#define PCS_PARTNER_ABILITY_1000BASE_X_PS2 (1<<8) /* ro */
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/* Bits 9:11, Reserved. */ /* - */
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#define PCS_PARTNER_ABILITY_1000BASE_X_RF1 (1<<12) /* ro */
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#define PCS_PARTNER_ABILITY_1000BASE_X_RF2 (1<<13) /* ro */
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#define PCS_PARTNER_ABILITY_1000BASE_X_ACK (1<<14) /* ro */
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#define PCS_PARTNER_ABILITY_1000BASE_X_NP (1<<15) /* ro */
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/* SGMII */
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/* Bits 0:9, Reserved. */ /* - */
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#define PCS_PARTNER_ABILITY_SGMII_COPPER_SPEED0 (1<<10) /* ro */
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#define PCS_PARTNER_ABILITY_SGMII_COPPER_SPEED1 (1<<11) /* ro */
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#define PCS_PARTNER_ABILITY_SGMII_COPPER_DUPLEX_STATUS (1<<12) /* ro */
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/* Bit 13, Reserved. */ /* - */
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#define PCS_PARTNER_ABILITY_SGMII_ACK (1<<14) /* ro */
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#define PCS_PARTNER_ABILITY_SGMII_COPPER_LINK_STATUS (1<<15) /* ro */
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#define PCS_AN_EXPANSION 0x06 /* ro */
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#define PCS_AN_EXPANSION_LINK_PARTNER_AUTO_NEGOTIATION_ABLE (1<<0) /* ro */
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#define PCS_AN_EXPANSION_PAGE_RECEIVE (1<<1) /* ro */
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#define PCS_AN_EXPANSION_NEXT_PAGE_ABLE (1<<2) /* -, 0 */
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/* Bits 3:15, Reserved. */ /* - */
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#define PCS_DEVICE_NEXT_PAGE 0x07 /* ro */
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#define PCS_PARTNER_NEXT_PAGE 0x08 /* ro */
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#define PCS_MASTER_SLAVE_CNTL 0x09 /* ro */
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#define PCS_MASTER_SLAVE_STAT 0x0A /* ro */
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/* 0x0B - 0x0E, Reserved */ /* - */
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#define PCS_EXTENDED_STATUS 0x0F /* ro */
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/* Specific Extended Registers. */
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#define PCS_EXT_SCRATCH 0x10 /* rw */
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#define PCS_EXT_REV 0x11 /* ro */
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#define PCS_EXT_LINK_TIMER_0 0x12 /* rw */
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#define PCS_EXT_LINK_TIMER_1 0x13 /* rw */
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#define PCS_EXT_IF_MODE 0x14 /* rw */
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#define PCS_EXT_IF_MODE_SGMII_ENA (1<<0) /* rw */
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#define PCS_EXT_IF_MODE_USE_SGMII_AN (1<<1) /* rw */
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#define PCS_EXT_IF_MODE_SGMII_SPEED1 (1<<2) /* rw */
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#define PCS_EXT_IF_MODE_SGMII_SPEED0 (1<<3) /* rw */
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#define PCS_EXT_IF_MODE_SGMII_DUPLEX (1<<4) /* rw */
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/* Bits 5:15, Reserved. */ /* - */
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|
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#define PCS_EXT_DISABLE_READ_TIMEOUT 0x15 /* rw */
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#define PCS_EXT_READ_TIMEOUT 0x16 /* r0 */
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/* 0x17-0x1F, Reserved. */
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|
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/* 0xA0 - 0xBF, MDIO Space 1. */
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#define MDIO_1_START 0xA0
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#define ATSE_BMCR MDIO_1_START
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/* 0xC0 - 0xC7, Supplementary Address. */
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#define SUPPL_ADDR_SMAC_0_0 0xC0 /* rw */
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#define SUPPL_ADDR_SMAC_0_1 0xC1 /* rw */
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#define SUPPL_ADDR_SMAC_1_0 0xC2 /* rw */
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#define SUPPL_ADDR_SMAC_1_1 0xC3 /* rw */
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#define SUPPL_ADDR_SMAC_2_0 0xC4 /* rw */
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#define SUPPL_ADDR_SMAC_2_1 0xC5 /* rw */
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#define SUPPL_ADDR_SMAC_3_0 0xC6 /* rw */
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#define SUPPL_ADDR_SMAC_3_1 0xC7 /* rw */
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|
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/* 0xC8 - 0xCF, Reserved; set to zero, ignore on read. */
|
|
/* 0xD7 - 0xFF, Reserved; set to zero, ignore on read. */
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|
|
|
|
|
/* -------------------------------------------------------------------------- */
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|
|
|
/* DE4 Intel Strata Flash Ethernet Option Bits area. */
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|
/* XXX-BZ this is something a loader will have to handle for us. */
|
|
#define ALTERA_ETHERNET_OPTION_BITS_OFF 0x00008000
|
|
#define ALTERA_ETHERNET_OPTION_BITS_LEN 0x00007fff
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|
|
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/* -------------------------------------------------------------------------- */
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|
|
|
struct atse_softc {
|
|
struct ifnet *atse_ifp;
|
|
struct mbuf *atse_rx_m;
|
|
struct mbuf *atse_tx_m;
|
|
uint8_t *atse_tx_buf;
|
|
struct resource *atse_mem_res;
|
|
struct resource *atse_rx_irq_res;
|
|
struct resource *atse_rx_mem_res;
|
|
struct resource *atse_rxc_mem_res;
|
|
struct resource *atse_tx_irq_res;
|
|
struct resource *atse_tx_mem_res;
|
|
struct resource *atse_txc_mem_res;
|
|
device_t atse_miibus;
|
|
device_t atse_dev;
|
|
int atse_unit;
|
|
int atse_mem_rid;
|
|
int atse_rx_irq_rid;
|
|
int atse_rx_mem_rid;
|
|
int atse_rxc_mem_rid;
|
|
int atse_tx_irq_rid;
|
|
int atse_tx_mem_rid;
|
|
int atse_txc_mem_rid;
|
|
int atse_phy_addr;
|
|
int atse_if_flags;
|
|
int atse_rx_irq;
|
|
int atse_tx_irq;
|
|
u_long atse_rx_maddr;
|
|
u_long atse_rx_msize;
|
|
u_long atse_tx_maddr;
|
|
u_long atse_tx_msize;
|
|
u_long atse_rxc_maddr;
|
|
u_long atse_rxc_msize;
|
|
u_long atse_txc_maddr;
|
|
u_long atse_txc_msize;
|
|
void *atse_rx_intrhand;
|
|
void *atse_tx_intrhand;
|
|
bus_addr_t atse_bmcr0;
|
|
bus_addr_t atse_bmcr1;
|
|
uint32_t atse_flags;
|
|
#define ATSE_FLAGS_LINK 0x00000001
|
|
#define ATSE_FLAGS_ERROR 0x00000002
|
|
#define ATSE_FLAGS_SOP_SEEN 0x00000004
|
|
uint8_t atse_eth_addr[ETHER_ADDR_LEN];
|
|
#define ATSE_ETH_ADDR_DEF 0x01
|
|
#define ATSE_ETH_ADDR_SUPP1 0x02
|
|
#define ATSE_ETH_ADDR_SUPP2 0x04
|
|
#define ATSE_ETH_ADDR_SUPP3 0x08
|
|
#define ATSE_ETH_ADDR_SUPP4 0x10
|
|
#define ATSE_ETH_ADDR_ALL 0x1f
|
|
uint16_t atse_watchdog_timer;
|
|
uint16_t atse_tx_m_offset;
|
|
uint16_t atse_tx_buf_len;
|
|
uint16_t atse_rx_buf_len;
|
|
int16_t atse_rx_cycles; /* POLLING */
|
|
#define RX_CYCLES_IN_INTR 5
|
|
uint32_t atse_rx_err[6];
|
|
#define ATSE_RX_ERR_FIFO_THRES_EOP 0 /* FIFO threshold reached, on EOP. */
|
|
#define ATSE_RX_ERR_ELEN 1 /* Frame/payload length not valid. */
|
|
#define ATSE_RX_ERR_CRC32 2 /* CRC-32 error. */
|
|
#define ATSE_RX_ERR_FIFO_THRES_TRUNC 3 /* FIFO thresh., truncated frame. */
|
|
#define ATSE_RX_ERR_4 4 /* ? */
|
|
#define ATSE_RX_ERR_5 5 /* / */
|
|
#define ATSE_RX_ERR_MAX 6
|
|
struct callout atse_tick;
|
|
struct mtx atse_mtx;
|
|
};
|
|
|
|
|
|
int atse_attach(device_t);
|
|
int atse_detach_dev(device_t);
|
|
void atse_detach_resources(device_t);
|
|
|
|
int atse_miibus_readreg(device_t, int, int);
|
|
int atse_miibus_writereg(device_t, int, int, int);
|
|
void atse_miibus_statchg(device_t);
|
|
|
|
extern devclass_t atse_devclass;
|
|
|
|
#endif /* _DEV_IF_ATSEREG_H */
|
|
|
|
/* end */
|