272 lines
11 KiB
C
272 lines
11 KiB
C
/*-
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********************************************************************************
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Copyright (C) 2015 Annapurna Labs Ltd.
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This file may be licensed under the terms of the Annapurna Labs Commercial
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License Agreement.
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Alternatively, this file can be distributed under the terms of the GNU General
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Public License V2 as published by the Free Software Foundation and can be
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found at http://www.gnu.org/licenses/gpl-2.0.html
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Alternatively, redistribution and use in source and binary forms, with or
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without modification, are permitted provided that the following conditions are
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met:
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* Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in
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the documentation and/or other materials provided with the
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distribution.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************/
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#ifndef _AL_HAL_PCIE_INTERRUPTS_H_
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#define _AL_HAL_PCIE_INTERRUPTS_H_
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#include "al_hal_common.h"
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#include "al_hal_pcie.h"
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#include "al_hal_iofic.h"
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/**
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* @defgroup group_pcie_interrupts PCIe interrupts
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* @ingroup grouppcie
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* @{
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* The PCIe interrupts HAL can be used to control PCIe unit interrupts.
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* There are 5 groups of interrupts: app group A, B, C, D and AXI.
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* Only 2 interrupts go from the pcie unit to the GIC:
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* 1. Summary for all the int groups (AXI+APP CORE).
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* 2. INTA assert/deassert (RC only).
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* For the specific GIC interrupt line, please check the architecture reference
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* manual.
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* The reset mask state of all interrupts is: Masked
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*
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* @file al_hal_pcie_interrupts.h
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*
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*/
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/**
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* PCIe interrupt groups
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*/
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enum al_pcie_int_group {
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AL_PCIE_INT_GRP_A,
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AL_PCIE_INT_GRP_B,
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AL_PCIE_INT_GRP_C, /* Rev3 only */
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AL_PCIE_INT_GRP_D, /* Rev3 only */
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AL_PCIE_INT_GRP_AXI_A,
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};
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/**
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* App group A interrupts mask - don't change
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* All interrupts not listed below should be masked
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*/
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enum al_pcie_app_int_grp_a {
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/** [RC only] Deassert_INTD received */
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AL_PCIE_APP_INT_DEASSERT_INTD = AL_BIT(0),
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/** [RC only] Deassert_INTC received */
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AL_PCIE_APP_INT_DEASSERT_INTC = AL_BIT(1),
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/** [RC only] Deassert_INTB received */
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AL_PCIE_APP_INT_DEASSERT_INTB = AL_BIT(2),
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/**
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* [RC only] Deassert_INTA received - there's a dedicated GIC interrupt
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* line that reflects the status of ASSERT/DEASSERT of INTA
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*/
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AL_PCIE_APP_INT_DEASSERT_INTA = AL_BIT(3),
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/** [RC only] Assert_INTD received */
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AL_PCIE_APP_INT_ASSERT_INTD = AL_BIT(4),
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/** [RC only] Assert_INTC received */
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AL_PCIE_APP_INT_ASSERT_INTC = AL_BIT(5),
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/** [RC only] Assert_INTB received */
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AL_PCIE_APP_INT_ASSERT_INTB = AL_BIT(6),
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/**
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* [RC only] Assert_INTA received - there's a dedicated GIC interrupt
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* line that reflects the status of ASSERT/DEASSERT of INTA
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*/
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AL_PCIE_APP_INT_ASSERT_INTA = AL_BIT(7),
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/** [RC only] MSI Controller Interrupt */
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AL_PCIE_APP_INT_MSI_CNTR_RCV_INT = AL_BIT(8),
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/** [EP only] MSI sent grant */
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AL_PCIE_APP_INT_MSI_TRNS_GNT = AL_BIT(9),
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/** [RC only] System error detected (ERR_COR, ERR_FATAL, ERR_NONFATAL) */
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AL_PCIE_APP_INT_SYS_ERR_RC = AL_BIT(10),
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/** [EP only] Software initiates FLR on a Physical Function */
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AL_PCIE_APP_INT_FLR_PF_ACTIVE = AL_BIT(11),
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/** [RC only] Root Error Command register assertion notification */
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AL_PCIE_APP_INT_AER_RC_ERR = AL_BIT(12),
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/** [RC only] Root Error Command register assertion notification With MSI or MSIX enabled */
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AL_PCIE_APP_INT_AER_RC_ERR_MSI = AL_BIT(13),
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/** [RC only] PME Status bit assertion in the Root Status register With INTA */
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AL_PCIE_APP_INT_PME_INT = AL_BIT(15),
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/** [RC only] PME Status bit assertion in the Root Status register With MSI or MSIX enabled */
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AL_PCIE_APP_INT_PME_MSI = AL_BIT(16),
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/** [RC/EP] The core assert link down event, whenever the link is going down */
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AL_PCIE_APP_INT_LINK_DOWN = AL_BIT(21),
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/** [EP only] When the EP gets a command to shut down, signal the software to block any new TLP. */
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AL_PCIE_APP_INT_PM_XTLH_BLOCK_TLP = AL_BIT(22),
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/** [RC/EP] PHY/MAC link up */
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AL_PCIE_APP_INT_XMLH_LINK_UP = AL_BIT(23),
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/** [RC/EP] Data link up */
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AL_PCIE_APP_INT_RDLH_LINK_UP = AL_BIT(24),
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/** [RC/EP] The LTSSM is in RCVRY_LOCK state. */
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AL_PCIE_APP_INT_LTSSM_RCVRY_STATE = AL_BIT(25),
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/**
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* [RC/EP] CFG write transaction to the configuration space by the RC peer
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* For RC the int/ will be set from DBI write (internal SoC write)]
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*/
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AL_PCIE_APP_INT_CFG_WR = AL_BIT(26),
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/** [EP only] CFG access in EP mode */
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AL_PCIE_APP_INT_CFG_ACCESS = AL_BIT(31),
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};
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/**
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* App group B interrupts mask - don't change
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* All interrupts not listed below should be masked
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*/
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enum al_pcie_app_int_grp_b {
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/** [RC only] PM_PME Message received */
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AL_PCIE_APP_INT_GRP_B_PM_PME_MSG_RCVD = AL_BIT(0),
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/** [RC only] PME_TO_Ack Message received */
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AL_PCIE_APP_INT_GRP_B_PME_TO_ACK_MSG_RCVD = AL_BIT(1),
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/** [EP only] PME_Turn_Off Message received */
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AL_PCIE_APP_INT_GRP_B_PME_TURN_OFF_MSG_RCVD = AL_BIT(2),
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/** [RC only] ERR_CORR Message received */
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AL_PCIE_APP_INT_GRP_B_CORR_ERR_MSG_RCVD = AL_BIT(3),
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/** [RC only] ERR_NONFATAL Message received */
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AL_PCIE_APP_INT_GRP_B_NON_FTL_ERR_MSG_RCVD = AL_BIT(4),
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/** [RC only] ERR_FATAL Message received */
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AL_PCIE_APP_INT_GRP_B_FTL_ERR_MSG_RCVD = AL_BIT(5),
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/**
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* [RC/EP] Vendor Defined Message received
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* Asserted when a vendor message is received (with no data), buffers 2
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* messages only, and latch the headers in registers
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*/
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AL_PCIE_APP_INT_GRP_B_VNDR_MSG_A_RCVD = AL_BIT(6),
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/**
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* [RC/EP] Vendor Defined Message received
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* Asserted when a vendor message is received (with no data), buffers 2
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* messages only, and latch the headers in registers
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*/
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AL_PCIE_APP_INT_GRP_B_VNDR_MSG_B_RCVD = AL_BIT(7),
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/** [EP only] Link Autonomous Bandwidth Status is updated */
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AL_PCIE_APP_INT_GRP_B_LNK_BW_UPD = AL_BIT(12),
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/** [EP only] Link Equalization Request bit in the Link Status 2 Register has been set */
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AL_PCIE_APP_INT_GRP_B_LNK_EQ_REQ = AL_BIT(13),
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/** [RC/EP] OB Vendor message request is granted by the PCIe core */
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AL_PCIE_APP_INT_GRP_B_OB_VNDR_MSG_REQ_GRNT = AL_BIT(14),
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/** [RC only] CPL timeout from the PCIe core indication */
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AL_PCIE_APP_INT_GRP_B_CPL_TO = AL_BIT(15),
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/** [RC/EP] Slave Response Composer Lookup Error */
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AL_PCIE_APP_INT_GRP_B_SLV_RESP_COMP_LKUP_ERR = AL_BIT(16),
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/** [RC/EP] Parity Error */
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AL_PCIE_APP_INT_GRP_B_PARITY_ERR = AL_BIT(17),
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/** [EP only] Speed change request */
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AL_PCIE_APP_INT_GRP_B_SPEED_CHANGE = AL_BIT(31),
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};
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/**
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* AXI interrupts mask - don't change
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* These are internal errors that can happen on the internal chip interface
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* between the PCIe port and the I/O Fabric over the AXI bus. The notion of
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* master and slave refer to the PCIe port master interface towards the I/O
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* Fabric (i.e. for inbound PCIe writes/reads toward the I/O Fabric), while the
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* slave interface refer to the I/O Fabric to PCIe port interface where the
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* internal chip DMAs and CPU cluster is initiating transactions.
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* All interrupts not listed below should be masked.
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*/
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enum al_pcie_axi_int {
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/** [RC/EP] Master Response Composer Lookup Error */
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AL_PCIE_AXI_INT_MSTR_RESP_COMP_LKUP_ERR = AL_BIT(0),
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/** [RC/EP] PARITY ERROR on the master data read channel */
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AL_PCIE_AXI_INT_PARITY_ERR_MSTR_DATA_RD_CHNL = AL_BIT(2),
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/** [RC/EP] PARITY ERROR on the slave addr read channel */
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AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_RD_CHNL = AL_BIT(3),
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/** [RC/EP] PARITY ERROR on the slave addr write channel */
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AL_PCIE_AXI_INT_PARITY_ERR_SLV_ADDR_WR_CHNL = AL_BIT(4),
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/** [RC/EP] PARITY ERROR on the slave data write channel */
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AL_PCIE_AXI_INT_PARITY_ERR_SLV_DATA_WR_CHNL = AL_BIT(5),
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/** [RC only] Software error: ECAM write request with invalid bus number */
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AL_PCIE_AXI_INT_ECAM_WR_REQ_INVLD_BUS_NUM = AL_BIT(7),
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/** [RC only] Software error: ECAM read request with invalid bus number */
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AL_PCIE_AXI_INT_ECAM_RD_REQ_INVLD_BUS_NUM = AL_BIT(8),
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/** [RC/EP] Read AXI completion has ERROR */
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AL_PCIE_AXI_INT_RD_AXI_COMPL_ERR = AL_BIT(11),
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/** [RC/EP] Write AXI completion has ERROR */
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AL_PCIE_AXI_INT_WR_AXI_COMPL_ERR = AL_BIT(12),
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/** [RC/EP] Read AXI completion has timed out */
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AL_PCIE_AXI_INT_RD_AXI_COMPL_TO = AL_BIT(13),
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/** [RC/EP] Write AXI completion has timed out */
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AL_PCIE_AXI_INT_WR_AXI_COMPL_TO = AL_BIT(14),
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/** [RC/EP] Parity error AXI domain */
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AL_PCIE_AXI_INT_AXI_DOM_PARITY_ERR = AL_BIT(15),
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/** [RC/EP] POS error interrupt */
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AL_PCIE_AXI_INT_POS_ERR = AL_BIT(16),
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};
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/**
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* @brief Initialize and configure PCIe controller interrupts
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* Doesn't change the mask state of the interrupts
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* The reset mask state of all interrupts is: Masked
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*
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* @param pcie_port pcie port handle
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*/
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void al_pcie_ints_config(struct al_pcie_port *pcie_port);
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/**
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* Unmask PCIe app group interrupts
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* @param pcie_port pcie_port pcie port handle
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* @param int_group interrupt group
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* @param int_mask int_mask interrupts to unmask ('1' to unmask)
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*/
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void al_pcie_app_int_grp_unmask(
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struct al_pcie_port *pcie_port,
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enum al_pcie_int_group int_group,
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uint32_t int_mask);
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/**
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* Mask PCIe app group interrupts
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* @param pcie_port pcie_port pcie port handle
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* @param int_group interrupt group
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* @param int_mask int_mask interrupts to unmask ('1' to mask)
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*/
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void al_pcie_app_int_grp_mask(
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struct al_pcie_port *pcie_port,
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enum al_pcie_int_group int_group,
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uint32_t int_mask);
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/**
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* Clear the PCIe app group interrupt cause
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* @param pcie_port pcie port handle
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* @param int_group interrupt group
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* @param int_cause interrupt cause
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*/
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void al_pcie_app_int_grp_cause_clear(
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struct al_pcie_port *pcie_port,
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enum al_pcie_int_group int_group,
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uint32_t int_cause);
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/**
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* Read PCIe app group interrupt cause
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* @param pcie_port pcie port handle
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* @param int_group interrupt group
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* @return interrupt cause or 0 in case the group is not supported
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*/
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uint32_t al_pcie_app_int_grp_cause_read(
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struct al_pcie_port *pcie_port,
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enum al_pcie_int_group int_group);
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#endif
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/** @} end of group_pcie_interrupts group */
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