414 lines
12 KiB
C
414 lines
12 KiB
C
/*-
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* Copyright (C) 2009-2012 Semihalf
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_NAND_H_
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#define _DEV_NAND_H_
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#include <sys/bus.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/lock.h>
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#include <sys/sx.h>
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#include <sys/taskqueue.h>
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#include <sys/queue.h>
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#include <sys/bio.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/malloc.h>
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#include <dev/nand/nand_dev.h>
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MALLOC_DECLARE(M_NAND);
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/* Read commands */
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#define NAND_CMD_READ 0x00
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#define NAND_CMD_CHNG_READ_COL 0x05
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#define NAND_CMD_READ_END 0x30
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#define NAND_CMD_READ_CACHE 0x31
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#define NAND_CMD_READ_CPBK 0x35
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#define NAND_CMD_READ_CACHE_END 0x3F
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#define NAND_CMD_CHNG_READ_COL_END 0xE0
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/* Erase commands */
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#define NAND_CMD_ERASE 0x60
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#define NAND_CMD_ERASE_END 0xD0
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#define NAND_CMD_ERASE_INTLV 0xD1
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/* Program commands */
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#define NAND_CMD_PROG 0x80
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#define NAND_CMD_CHNG_WRITE_COL 0x85
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#define NAND_CMD_PROG_END 0x10
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#define NAND_CMD_PROG_INTLV 0x11
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#define NAND_CMD_PROG_CACHE 0x15
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/* Misc commands */
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#define NAND_CMD_STATUS 0x70
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#define NAND_CMD_STATUS_ENH 0x78
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#define NAND_CMD_READ_ID 0x90
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#define NAND_CMD_READ_PARAMETER 0xec
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#define NAND_CMD_READ_UNIQUE_ID 0xed
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#define NAND_CMD_GET_FEATURE 0xee
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#define NAND_CMD_SET_FEATURE 0xef
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/* Reset commands */
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#define NAND_CMD_SYNCH_RESET 0xfc
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#define NAND_CMD_RESET 0xff
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/* Small page flash commands */
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#define NAND_CMD_SMALLA 0x00
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#define NAND_CMD_SMALLB 0x01
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#define NAND_CMD_SMALLOOB 0x50
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#define NAND_STATUS_FAIL 0x1
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#define NAND_STATUS_FAILC 0x2
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#define NAND_STATUS_ARDY 0x20
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#define NAND_STATUS_RDY 0x40
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#define NAND_STATUS_WP 0x80
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#define NAND_LP_OOB_COLUMN_START 0x800
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#define NAND_LP_OOBSZ 0x40
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#define NAND_SP_OOB_COLUMN_START 0x200
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#define NAND_SP_OOBSZ 0x10
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#define PAGE_PARAM_LENGTH 0x100
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#define PAGE_PARAMETER_DEF 0x0
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#define PAGE_PARAMETER_RED_1 0x100
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#define PAGE_PARAMETER_RED_2 0x200
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#define ONFI_SIG_ADDR 0x20
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#define NAND_MAX_CHIPS 0x4
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#define NAND_MAX_OOBSZ 512
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#define NAND_MAX_PAGESZ 16384
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#define NAND_SMALL_PAGE_SIZE 0x200
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#define NAND_16_BIT 0x00000001
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#define NAND_ECC_NONE 0x0
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#define NAND_ECC_SOFT 0x1
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#define NAND_ECC_FULLHW 0x2
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#define NAND_ECC_PARTHW 0x4
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#define NAND_ECC_MODE_MASK 0x7
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#define ECC_OK 0
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#define ECC_CORRECTABLE 1
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#define ECC_ERROR_ECC (-1)
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#define ECC_UNCORRECTABLE (-2)
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#define NAND_MAN_SAMSUNG 0xec
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#define NAND_MAN_HYNIX 0xad
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#define NAND_MAN_STMICRO 0x20
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#define NAND_MAN_MICRON 0x2c
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struct nand_id {
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uint8_t man_id;
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uint8_t dev_id;
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};
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struct nand_params {
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struct nand_id id;
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char *name;
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uint32_t chip_size;
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uint32_t page_size;
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uint32_t oob_size;
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uint32_t pages_per_block;
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uint32_t flags;
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};
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/* nand debug levels */
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#define NDBG_NAND 0x01
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#define NDBG_CDEV 0x02
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#define NDBG_GEN 0x04
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#define NDBG_GEOM 0x08
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#define NDBG_BUS 0x10
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#define NDBG_SIM 0x20
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#define NDBG_CTRL 0x40
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#define NDBG_DRV 0x80
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#define NDBG_ECC 0x100
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/* nand_debug_function */
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void nand_debug(int level, const char *fmt, ...);
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extern int nand_debug_flag;
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/* ONFI features bit*/
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#define ONFI_FEAT_16BIT 0x01
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#define ONFI_FEAT_MULT_LUN 0x02
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#define ONFI_FEAT_INTLV_OPS 0x04
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#define ONFI_FEAT_CPBK_RESTRICT 0x08
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#define ONFI_FEAT_SRC_SYNCH 0x10
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/* ONFI optional commands bits */
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#define ONFI_OPTCOM_PROG_CACHE 0x01
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#define ONFI_OPTCOM_READ_CACHE 0x02
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#define ONFI_OPTCOM_GETSET_FEAT 0x04
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#define ONFI_OPTCOM_STATUS_ENH 0x08
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#define ONFI_OPTCOM_COPYBACK 0x10
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#define ONFI_OPTCOM_UNIQUE_ID 0x20
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/* Layout of parameter page is defined in ONFI */
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struct onfi_params {
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char signature[4];
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uint16_t rev;
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uint16_t features;
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uint16_t optional_commands;
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uint8_t primary_advanced_command;
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uint8_t res1;
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uint16_t extended_parameter_page_length;
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uint8_t parameter_page_count;
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uint8_t res2[17];
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char manufacturer_name[12];
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char device_model[20];
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uint8_t manufacturer_id;
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uint8_t manufacture_date_yy;
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uint8_t manufacture_date_ww;
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uint8_t res3[13];
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uint32_t bytes_per_page;
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uint16_t spare_bytes_per_page;
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uint32_t bytes_per_partial_page;
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uint16_t spare_bytes_per_partial_page;
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uint32_t pages_per_block;
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uint32_t blocks_per_lun;
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uint8_t luns;
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uint8_t address_cycles;
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uint8_t bits_per_cell;
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uint16_t max_bad_block_per_lun;
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uint16_t block_endurance;
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uint8_t guaranteed_valid_blocks;
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uint16_t valid_block_endurance;
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uint8_t programs_per_page;
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uint8_t partial_prog_attr;
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uint8_t bits_of_ecc;
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uint8_t interleaved_addr_bits;
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uint8_t interleaved_oper_attr;
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uint8_t eznand_support;
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uint8_t res4[12];
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uint8_t pin_capacitance;
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uint16_t asynch_timing_mode_support;
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uint16_t asynch_prog_cache_timing_mode_support;
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uint16_t t_prog; /* us, max page program time */
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uint16_t t_bers; /* us, max block erase time */
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uint16_t t_r; /* us, max page read time */
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uint16_t t_ccs; /* ns, min change column setup time */
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uint16_t source_synch_timing_mode_support;
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uint8_t source_synch_feat;
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uint16_t clk_input_capacitance;
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uint16_t io_capacitance;
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uint16_t input_capacitance;
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uint8_t input_capacitance_max;
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uint8_t driver_strength_support;
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uint16_t t_r_interleaved;
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uint16_t t_adl;
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uint16_t t_r_eznand;
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uint8_t nv_ddr2_features;
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uint8_t nv_ddr2_warmup_cycles;
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uint8_t res5[4];
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uint16_t vendor_rev;
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uint8_t vendor_spec[88];
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uint16_t crc;
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}__attribute__((packed));
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CTASSERT(sizeof(struct onfi_params) == 256);
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struct onfi_chip_params {
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uint32_t blocks_per_lun;
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uint32_t pages_per_block;
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uint32_t bytes_per_page;
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uint32_t spare_bytes_per_page;
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uint16_t t_bers;
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uint16_t t_prog;
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uint16_t t_r;
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uint16_t t_ccs;
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uint16_t features;
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uint8_t address_cycles;
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uint8_t luns;
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};
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struct nand_ecc_data {
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int eccsize; /* Number of data bytes per ECC step */
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int eccmode;
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int eccbytes; /* Number of ECC bytes per step */
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uint16_t *eccpositions; /* Positions of ecc bytes */
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uint8_t ecccalculated[NAND_MAX_OOBSZ];
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uint8_t eccread[NAND_MAX_OOBSZ];
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};
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struct ecc_stat {
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uint32_t ecc_succeded;
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uint32_t ecc_corrected;
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uint32_t ecc_failed;
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};
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struct page_stat {
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struct ecc_stat ecc_stat;
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uint32_t page_read;
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uint32_t page_raw_read;
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uint32_t page_written;
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uint32_t page_raw_written;
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};
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struct block_stat {
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uint32_t block_erased;
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};
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struct chip_geom {
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uint32_t chip_size;
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uint32_t block_size;
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uint32_t page_size;
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uint32_t oob_size;
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uint32_t luns;
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uint32_t blks_per_lun;
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uint32_t blks_per_chip;
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uint32_t pgs_per_blk;
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uint32_t pg_mask;
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uint32_t blk_mask;
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uint32_t lun_mask;
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uint8_t blk_shift;
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uint8_t lun_shift;
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};
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struct nand_chip {
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device_t dev;
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struct nand_id id;
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struct chip_geom chip_geom;
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uint16_t t_prog; /* us, max page program time */
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uint16_t t_bers; /* us, max block erase time */
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uint16_t t_r; /* us, max page read time */
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uint16_t t_ccs; /* ns, min change column setup time */
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uint8_t num;
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uint8_t flags;
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struct page_stat *pg_stat;
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struct block_stat *blk_stat;
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struct nand_softc *nand;
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struct nand_bbt *bbt;
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struct nand_ops *ops;
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struct cdev *cdev;
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struct disk *ndisk;
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struct disk *rdisk;
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struct bio_queue_head bioq; /* bio queue */
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struct mtx qlock; /* bioq lock */
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struct taskqueue *tq; /* private task queue for i/o request */
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struct task iotask; /* i/o processing */
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};
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struct nand_softc {
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uint8_t flags;
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char *chip_cdev_name;
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struct nand_ecc_data ecc;
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};
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/* NAND ops */
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int nand_erase_blocks(struct nand_chip *chip, off_t offset, size_t len);
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int nand_prog_pages(struct nand_chip *chip, uint32_t offset, uint8_t *buf,
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uint32_t len);
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int nand_read_pages(struct nand_chip *chip, uint32_t offset, void *buf,
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uint32_t len);
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int nand_read_pages_raw(struct nand_chip *chip, uint32_t offset, void *buf,
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uint32_t len);
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int nand_prog_pages_raw(struct nand_chip *chip, uint32_t offset, void *buf,
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uint32_t len);
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int nand_read_oob(struct nand_chip *chip, uint32_t page, void *buf,
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uint32_t len);
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int nand_prog_oob(struct nand_chip *chip, uint32_t page, void *buf,
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uint32_t len);
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int nand_select_cs(device_t dev, uint8_t cs);
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int nand_read_parameter(struct nand_softc *nand, struct onfi_params *param);
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int nand_synch_reset(struct nand_softc *nand);
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int nand_chng_read_col(device_t dev, uint32_t col, void *buf, size_t len);
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int nand_chng_write_col(device_t dev, uint32_t col, void *buf, size_t len);
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int nand_get_feature(device_t dev, uint8_t feat, void* buf);
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int nand_set_feature(device_t dev, uint8_t feat, void* buf);
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int nand_erase_block_intlv(device_t dev, uint32_t block);
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int nand_copyback_read(device_t dev, uint32_t page, uint32_t col,
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void *buf, size_t len);
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int nand_copyback_prog(device_t dev, uint32_t page, uint32_t col,
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void *buf, size_t len);
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int nand_copyback_prog_intlv(device_t dev, uint32_t page);
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int nand_prog_cache(device_t dev, uint32_t page, uint32_t col,
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void *buf, size_t len, uint8_t end);
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int nand_prog_intlv(device_t dev, uint32_t page, uint32_t col,
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void *buf, size_t len);
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int nand_read_cache(device_t dev, uint32_t page, uint32_t col,
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void *buf, size_t len, uint8_t end);
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int nand_write_ecc(struct nand_softc *nand, uint32_t page, uint8_t *data);
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int nand_read_ecc(struct nand_softc *nand, uint32_t page, uint8_t *data);
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int nand_softecc_get(device_t dev, uint8_t *buf, int pagesize, uint8_t *ecc);
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int nand_softecc_correct(device_t dev, uint8_t *buf, int pagesize,
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uint8_t *readecc, uint8_t *calcecc);
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/* Chip initialization */
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void nand_init(struct nand_softc *nand, device_t dev, int ecc_mode,
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int ecc_bytes, int ecc_size, uint16_t* eccposition, char* cdev_name);
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void nand_detach(struct nand_softc *nand);
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struct nand_params *nand_get_params(struct nand_id *id);
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void nand_onfi_set_params(struct nand_chip *chip, struct onfi_chip_params *params);
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void nand_set_params(struct nand_chip *chip, struct nand_params *params);
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int nand_init_stat(struct nand_chip *chip);
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void nand_destroy_stat(struct nand_chip *chip);
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/* BBT */
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int nand_init_bbt(struct nand_chip *chip);
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void nand_destroy_bbt(struct nand_chip *chip);
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int nand_update_bbt(struct nand_chip *chip);
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int nand_mark_bad_block(struct nand_chip* chip, uint32_t block_num);
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int nand_check_bad_block(struct nand_chip* chip, uint32_t block_num);
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/* cdev creation/removal */
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int nand_make_dev(struct nand_chip* chip);
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void nand_destroy_dev(struct nand_chip *chip);
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int create_geom_disk(struct nand_chip* chip);
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int create_geom_raw_disk(struct nand_chip *chip);
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void destroy_geom_disk(struct nand_chip *chip);
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void destroy_geom_raw_disk(struct nand_chip *chip);
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int init_chip_geom(struct chip_geom* cg, uint32_t luns, uint32_t blks_per_lun,
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uint32_t pgs_per_blk, uint32_t pg_size, uint32_t oob_size);
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int nand_row_to_blkpg(struct chip_geom *cg, uint32_t row, uint32_t *lun,
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uint32_t *blk, uint32_t *pg);
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int page_to_row(struct chip_geom *cg, uint32_t page, uint32_t *row);
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int nand_check_page_boundary(struct nand_chip *chip, uint32_t page);
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void nand_get_chip_param(struct nand_chip *chip, struct chip_param_io *param);
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#endif /* _DEV_NAND_H_ */
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