d/metal-cos
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Disable caching of PCI space, and progress on AHCI.

Browse Source
This commit is contained in:
Ali Mashtizadeh 2014-06-30 18:35:20 -07:00
parent 255f560351
commit 2b64bacc72
2 changed files with 97 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
sys/amd64/pmap.c
View File

@ -19,7 +19,7 @@ typedef struct AS
AS systemAS;
AS *currentAS[MAX_CPUS];
bool PMap_SystemLMap(uint64_t phys, uint64_t virt, uint64_t lpages);
bool PMap_SystemLMap(uint64_t phys, uint64_t virt, uint64_t lpages, uint64_t flags);
void PMapDump(AS *space);
void
@ -57,9 +57,11 @@ PMap_Init()
}
// Setup system mappings
// XXX XXX XXX
PMap_SystemLMap(0x0, 0x0, 0x100000000ULL >> LARGE_PGSHIFT);
//PMapDump(&systemAS);
PMap_SystemLMap(0x0, 0x0, (3*512), 0); // 3GB RWX
PMap_SystemLMap(0xC0000000, 0xC0000000, 512, PTE_NX|PTE_PCD); // 1GB RW + PCD
//PMap_SystemLMap(0x100000000ULL, 0x100000000ULL,
// 0x100000000ULL >> LARGE_PGSHIFT, 0); // Remaining
write_cr3((uint64_t)systemAS.root);
kprintf("Done!\n");
@ -224,7 +226,7 @@ PMapDump(AS *space)
}
bool
PMap_SystemLMap(uint64_t phys, uint64_t virt, uint64_t lpages)
PMap_SystemLMap(uint64_t phys, uint64_t virt, uint64_t lpages, uint64_t flags)
{
int i;
PageEntry *entry;
@ -237,7 +239,7 @@ PMap_SystemLMap(uint64_t phys, uint64_t virt, uint64_t lpages)
return false;
}
*entry = (phys + LARGE_PGSIZE * i) | PTE_P | PTE_W | PTE_PS;
*entry = (phys + LARGE_PGSIZE * i) | PTE_P | PTE_W | PTE_PS | flags;
//kprintf("SystemLMap VA: %08x, PTE: %08x\n", va, *entry);
}

89
sys/dev/ahci.c
View File

@ -17,6 +17,49 @@ static AHCIDevice deviceList[] =
{ 0, "", 0 },
};
typedef struct AHCIHostControl
{
uint32_t cap; // Host Capabilities
uint32_t ghc; // Global Host Control
uint32_t is; // Interrupt Status
uint32_t pi; // Ports Implemented
uint32_t vs; // Version
} AHCIHostControl;
#define AHCI_GHC_AE 0x80000000
#define AHCI_GHC_IE 0x00000002
#define AHCI_GHC_HR 0x00000001
typedef struct AHCIPort
{
uint64_t clba; // Command List Base Address
uint64_t fb; // FIS Base Address
uint32_t is; // Interrupt Status
uint32_t ie; // Interrupt Enable
uint32_t cmd; // Command
uint32_t _rsvd; // *Reserved*
uint32_t tfd; // Task File Data
uint32_t sig; // Signature
uint32_t ssts; // SATA Status
uint32_t sctl; // SATA Control
uint32_t serr; // SATA Error
uint32_t sact; // SATA Active
uint32_t ci; // Command Issue
uint32_t _rsvd2; // *Reserved*
} AHCIPort;
#define AHCI_ABAR 5
#define AHCI_PORT_OFFSET 0x100
#define AHCI_PORT_LENGTH 0x80
#define AHCI_MAX_PORTS 32
typedef struct AHCI
{
PCIDevice dev;
AHCIHostControl *hc;
AHCIPort *port[AHCI_MAX_PORTS];
} AHCI;
void AHCI_Configure(PCIDevice dev);
void
@ -51,9 +94,32 @@ AHCI_Init(uint32_t bus, uint32_t slot, uint32_t func)
}
}
void
AHCI_ResetPort(AHCI *ahci, int port)
{
}
void
AHCI_Reset(AHCI *ahci)
{
int port;
// Enable AHCI and Interrupts
ahci->hc->ghc = AHCI_GHC_AE | AHCI_GHC_IE;
// Reset ports
for (port = 0; port < AHCI_MAX_PORTS; port++)
{
if (ahci->port[port] != 0)
AHCI_ResetPort(ahci, port);
}
}
void
AHCI_Configure(PCIDevice dev)
{
AHCI ahci;
PCI_Configure(&dev);
kprintf("AHCI: IRQ %d\n", dev.irq);
@ -68,5 +134,28 @@ AHCI_Configure(PCIDevice dev)
bar, dev.bars[bar].base, dev.bars[bar].size,
dev.bars[bar].type == PCIBAR_TYPE_IO ? "IO" : "Mem");
}
// memcpy dev to ahci.dev
// Setup
ahci.hc = dev.bars[AHCI_ABAR].base;
uint32_t ports = ahci.hc->pi;
uint32_t vers = ahci.hc->vs;
kprintf("AHCI: Version %d.%d, Ports: 0x%08x\n",
vers >> 16, vers & 0xFFFF, ports);
int p;
for (p = 0; p < AHCI_MAX_PORTS; p++)
{
if (ports & (1 << p))
{
ahci.port[p] = dev.bars[AHCI_ABAR].base +
AHCI_PORT_OFFSET + AHCI_PORT_LENGTH * p;
} else {
ahci.port[p] = 0;
}
}
}