Improving AMD64 header
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@ -150,22 +150,21 @@ typedef struct PACKED TaskStateSegment64 {
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#define RFLAGS_CF 0x00000001 /* Carry Flag */
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#define RFLAGS_CF 0x00000001 /* Carry Flag */
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#define RFLAGS_PF 0x00000004 /* Parity Flag */
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#define RFLAGS_PF 0x00000004 /* Parity Flag */
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#define RFLAGS_AF
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#define RFLAGS_AF 0x00000010 /* Adjust Flag */
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#define RFLAGS_ZF
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#define RFLAGS_ZF 0x00000040 /* Zero Flag */
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#define RFLAGS_SF
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#define RFLAGS_SF 0x00000080 /* Sign Flag */
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#define RFLAGS_TF
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#define RFLAGS_TF 0x00000100 /* Trap Flag */
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#define RFLAGS_IF
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#define RFLAGS_IF 0x00000200 /* Interrupt Enable Flag */
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#define RFLAGS_DF
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#define RFLAGS_DF 0x00000400 /* Direction Flag */
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#define RFLAGS_OF
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#define RFLAGS_OF 0x00000800 /* Overflow Flag */
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// IOPL
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// IOPL (bits 12-13)
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#define RFLAGS_NT
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#define RFLAGS_NT 0x00004000 /* Nested Task Flag */
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#define RFLAGS_RF 0x00010000 /* Resume Flag */
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#define RFLAGS_RF 0x00010000
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#define RFLAGS_VM 0x00020000 /* Virtual 8086 Mode */
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#define RFLAGS_VM 0x00020000
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#define RFLAGS_AC 0x00040000 /* Alignment Check */
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#define RFLAGS_AC 0x00040000
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#define RFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */
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#define RFLAGS_VIF 0x00080000
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#define RFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */
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#define RFLAGS_VIP
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#define RFLAGS_ID 0x00200000 /* CPUID Supported */
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#define RFLAGS_ID
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/*
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/*
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* Debug Registers
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* Debug Registers
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@ -186,6 +185,12 @@ typedef struct PACKED TaskStateSegment64 {
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#define EFER_FFXSR 0x4000 /* Fast FXSAVE/FXRSTOR (AMD) */
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#define EFER_FFXSR 0x4000 /* Fast FXSAVE/FXRSTOR (AMD) */
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#define EFER_TCE 0x8000 /* Translation Cache Extension (AMD) */
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#define EFER_TCE 0x8000 /* Translation Cache Extension (AMD) */
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// SYSCALL/SYSRET
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#define MSR_STAR 0xC0000081
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#define MSR_LSTAR 0xC0000082
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#define MSR_CSTAR 0xC0000083
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#define MSR_SFMASK 0xC0000084
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#include "amd64op.h"
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#include "amd64op.h"
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#endif /* __AMD64_H__ */
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#endif /* __AMD64_H__ */
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@ -76,6 +76,11 @@ void Machine_SyscallInit()
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{
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{
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kprintf("Initializing Syscall... ");
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kprintf("Initializing Syscall... ");
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wrmsr(MSR_STAR, SEL_KCS << 32 | SEL_UCS << 48);
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wrmsr(MSR_LSTAR, 0);
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wrmsr(MSR_CSTAR, 0);
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wrmsr(MSR_SFMASK, 0);
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kprintf("Done!\n");
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kprintf("Done!\n");
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}
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}
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@ -2,25 +2,25 @@
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#ifndef __TRAP_H__
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#ifndef __TRAP_H__
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#define __TRAP_H__
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#define __TRAP_H__
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#define T_DE 0
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#define T_DE 0 /* Divide Error Exception */
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#define T_DB 1
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#define T_DB 1 /* Debug Exception */
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#define T_NMI 2
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#define T_NMI 2 /* NMI Interrupt */
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#define T_BP 3
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#define T_BP 3 /* Breakpoint Exception */
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#define T_OF 4
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#define T_OF 4 /* Overflow Exception */
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#define T_BR 5
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#define T_BR 5 /* BOUND Range Exceeded Exception */
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#define T_UD 6
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#define T_UD 6 /* Invalid Opcode Exception */
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#define T_NM 7
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#define T_NM 7 /* Device Not Available Exception */
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#define T_DF 8
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#define T_DF 8 /* Double Fault Exception */
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#define T_TS 10
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#define T_TS 10 /* Invalid TSS Exception */
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#define T_NP 11
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#define T_NP 11 /* Segment Not Present */
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#define T_SS 12
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#define T_SS 12 /* Stack Fault Exception */
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#define T_GP 13
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#define T_GP 13 /* General Protection Exception */
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#define T_PF 14
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#define T_PF 14 /* Page-Fault Exception */
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#define T_MF 16
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#define T_MF 16 /* x87 FPU Floating-Point Error */
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#define T_AC 17
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#define T_AC 17 /* Alignment Check Exception */
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#define T_MC 18
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#define T_MC 18 /* Machine-Check Exception */
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#define T_XF 19
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#define T_XF 19 /* SIMB Floating-Point Exception */
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#define T_VE 20
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#define T_VE 20 /* Virtualization Exception */
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#define T_CPU_LAST T_VE
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#define T_CPU_LAST T_VE
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@ -32,10 +32,14 @@
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#define T_IRQ_KBD (T_IRQ_BASE + 1)
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#define T_IRQ_KBD (T_IRQ_BASE + 1)
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#define T_IRQ_COM1 (T_IRQ_BASE + 4)
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#define T_IRQ_COM1 (T_IRQ_BASE + 4)
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#define T_IRQ_MOUSE (T_IRQ_BASE + 12)
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#define T_IRQ_MOUSE (T_IRQ_BASE + 12)
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// LAPIC Special Vectors
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#define T_IRQ_SPURIOUS (T_IRQ_BASE + 24)
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#define T_IRQ_SPURIOUS (T_IRQ_BASE + 24)
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#define T_IRQ_ERROR (T_IRQ_BASE + 25)
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#define T_IRQ_ERROR (T_IRQ_BASE + 25)
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#define T_IRQ_THERMAL (T_IRQ_BASE + 26)
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#define T_IRQ_THERMAL (T_IRQ_BASE + 26)
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#define T_SYSCALL 60
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#define T_MAX 64
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#define T_MAX 64
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typedef struct TrapFrame
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typedef struct TrapFrame
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