Built code to support issuing control commands.
This commit is contained in:
Ali Mashtizadeh
parent
f0b4968b62
commit
568d7ee600
202
sys/dev/ahci.c
202
sys/dev/ahci.c
@ -3,6 +3,41 @@
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#include <kassert.h>
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#include <pci.h>
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#include <sga.h>
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/*
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* SATA Definitions
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*/
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typedef struct SATAFIS_REG_H2D {
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uint8_t type; // 0x27
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uint8_t flag;
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uint8_t command;
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uint8_t feature0;
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uint8_t lba0;
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uint8_t lba1;
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uint8_t lba2;
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uint8_t device;
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uint8_t lba3;
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uint8_t lba4;
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uint8_t lba5;
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uint8_t feature1;
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uint8_t count0;
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uint8_t count1;
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uint8_t icc;
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uint8_t control;
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uint8_t _rsvd[4];
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} SATAFIS_REG_H2D;
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#define SATAFIS_REG_H2D_FLAG_COMMAND 0x80 /* Command Flag */
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#define SATAFIS_TYPE_REG_H2D 0x27
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#define SATAFIS_CMD_IDENTIFY 0xEC
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/*
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* AHCI Definitions
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*/
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typedef struct AHCIDevice
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{
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@ -71,10 +106,20 @@ typedef struct AHCIPort
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#define AHCIPORT_CMD_SUD 0x00000002 /* Spin-Up Device */
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#define AHCIPORT_CMD_ST 0x00000001 /* Start */
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#define AHCIPORT_TFD_BSY 0x00000080 /* Port Busy */
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#define AHCIPORT_TFD_DRQ 0x00000004 /* Data Transfer Requested */
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#define AHCIPORT_TFD_ERR 0x00000001 /* Error during Transfer */
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#define AHCIPORT_SSTS_DETMASK 0x0000000F /* Device Detection (DET) Mask */
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#define AHCIPORT_SSTS_DETNP 0x00000000 /* DET: Not Present */
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#define AHCIPORT_SSTS_DETNOTEST 0x00000001 /* DET: Phy not established */
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#define AHCIPORT_SSTS_DETPE 0x00000003 /* DET: Present and Established */
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#define AHCIPORT_SSTS_DETNE 0x00000004 /* DET: Not Enabled or in BIST mode */
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#define AHCI_ABAR 5
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#define AHCI_PORT_OFFSET 0x100
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#define AHCI_PORT_LENGTH 0x80
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#define AHCI_MAX_PORTS 32
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#define AHCI_MAX_PORTS 8
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#define AHCI_MAX_CMDS 32
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/*
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@ -142,8 +187,10 @@ typedef struct AHCIRecvFIS
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typedef struct AHCI
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{
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PCIDevice dev;
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// Device Space
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AHCIHostControl *hc;
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AHCIPort *port[AHCI_MAX_PORTS];
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// Driver Memory
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AHCICommandList *clst[AHCI_MAX_PORTS];
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AHCICommandTable *ctbl[AHCI_MAX_PORTS][AHCI_MAX_CMDS];
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AHCIRecvFIS *rfis[AHCI_MAX_PORTS];
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@ -171,6 +218,12 @@ AHCI_Init(uint32_t bus, uint32_t slot, uint32_t func)
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return;
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}
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// XXX: Temporary until we have a slab allocator
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#define PGSIZE 4096
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ASSERT(sizeof(AHCI) <= PGSIZE);
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ASSERT(sizeof(AHCICommandList) <= PGSIZE);
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ASSERT(sizeof(AHCIRecvFIS) <= PGSIZE);
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int deviceIdx = 0;
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while (deviceList[deviceIdx].device != 0x0) {
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if (deviceList[deviceIdx].device == device) {
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@ -183,6 +236,78 @@ AHCI_Init(uint32_t bus, uint32_t slot, uint32_t func)
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}
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}
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uint64_t
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AHCI_IssueCommand(AHCI *ahci, int port, SGArray *sga, void *cfis, int len)
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{
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// XXX: support multiple commands
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volatile AHCICommandList *cl = ahci->clst[port];
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volatile AHCICommandTable *ct = ahci->ctbl[port][0];
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volatile AHCIPort *p = ahci->port[port];
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// Copy Command FIS
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memcpy(&ct->cfis, cfis, len);
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// Convert SGArray into PRDT
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int i;
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for (i = 0; i < sga->len; i++)
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{
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ct->prdt[i].dba = sga->entries[i].offset;
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ct->prdt[i].descInfo = sga->entries[i].length - 1;
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// Must be a multiple of word size
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ASSERT(sga->entries[i].length % 2 == 0);
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}
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// Specify cfis length and prdt entries;
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// XXX: support multiple commands
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cl->cmds[0].descInfo = (sga->len << 16) | (len / 4);
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p->ci = 1;
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}
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void
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AHCI_WaitPort(AHCI *ahci, int port)
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{
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volatile AHCIPort *p = ahci->port[port];
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while (1) {
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if (((p->tfd & AHCIPORT_TFD_BSY) == 0) && (p->ci != 0)) {
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return;
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}
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// implement timeouts
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}
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}
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void
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AHCI_IdentifyPort(AHCI *ahci, int port)
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{
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volatile AHCIPort *p = ahci->port[port];
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SGArray sga;
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SATAFIS_REG_H2D fis;
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uint8_t buf[512];
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kprintf("AHCI: Signature %08x\n", p->sig);
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memset(&fis, 0, sizeof(fis));
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fis.type = SATAFIS_TYPE_REG_H2D;
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fis.flag = SATAFIS_REG_H2D_FLAG_COMMAND;
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fis.command = SATAFIS_CMD_IDENTIFY;
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fis.count0 = 1;
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fis.count1 = 0;
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sga.len = 1;
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// VA2PA
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sga.entries[0].offset = &buf;
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sga.entries[0].length = 512;
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AHCI_IssueCommand(ahci, port, &sga, &fis, sizeof(fis));
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kprintf("AHCI: Identify Issued Port %d\n", port);
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AHCI_WaitPort(ahci, port);
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kprintf("AHCI: Identify Succeeded Port %d\n", port);
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return;
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}
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void
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AHCI_ResetPort(AHCI *ahci, int port)
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{
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@ -192,14 +317,14 @@ AHCI_ResetPort(AHCI *ahci, int port)
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AHCIPORT_CMD_FRE | AHCIPORT_CMD_FR;
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// Wait for controller to be idle
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if (cmd & cmd_mask != 0) {
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if ((cmd & cmd_mask) != 0) {
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int tries;
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for (tries = 0; tries < 2; tries++) {
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cmd = cmd & ~(AHCIPORT_CMD_ST | AHCIPORT_CMD_FRE);
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p->cmd = cmd;
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// sleep 500ms
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cmd = p->cmd;
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if (cmd & cmd_mask != 0) {
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if ((cmd & cmd_mask) != 0) {
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kprintf("AHCI: failed to reset port %d\n", port);
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}
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}
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@ -207,8 +332,22 @@ AHCI_ResetPort(AHCI *ahci, int port)
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// Reset error
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p->serr = 0xFFFFFFFF;
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p->serr = 0x00000000;
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//
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// Check port
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uint32_t ssts = p->ssts;
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if ((ssts & AHCIPORT_SSTS_DETMASK) == AHCIPORT_SSTS_DETNP) {
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kprintf("AHCI: Device not present on port %d\n", port);
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return;
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}
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if ((ssts & AHCIPORT_SSTS_DETMASK) == AHCIPORT_SSTS_DETNOTEST) {
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kprintf("AHCI: Phys communication not established on port %d\n", port);
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return;
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}
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if ((ssts & AHCIPORT_SSTS_DETNE) == AHCIPORT_SSTS_DETNOTEST) {
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kprintf("AHCI: Port %d not enabled\n", port);
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return;
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}
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}
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void
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@ -222,15 +361,18 @@ AHCI_Reset(AHCI *ahci)
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// Reset ports
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for (port = 0; port < AHCI_MAX_PORTS; port++)
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{
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if (ahci->port[port] != 0)
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if (ahci->port[port] != 0) {
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AHCI_ResetPort(ahci, port);
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// XXX: Skipme if nothing connected
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AHCI_IdentifyPort(ahci, port);
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}
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}
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}
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void
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AHCI_Configure(PCIDevice dev)
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{
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AHCI ahci;
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AHCI *ahci = (AHCI *)PAlloc_AllocPage();
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PCI_Configure(&dev);
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@ -247,27 +389,63 @@ AHCI_Configure(PCIDevice dev)
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dev.bars[bar].type == PCIBAR_TYPE_IO ? "IO" : "Mem");
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}
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// memcpy dev to ahci.dev
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// Copy PCIDevice structure
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memcpy(&ahci->dev, &dev, sizeof(dev));
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// XXX: Register IRQ
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// Setup
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ahci.hc = dev.bars[AHCI_ABAR].base;
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ahci->hc = dev.bars[AHCI_ABAR].base;
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uint32_t ports = ahci.hc->pi;
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uint32_t vers = ahci.hc->vs;
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uint32_t ports = ahci->hc->pi;
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uint32_t vers = ahci->hc->vs;
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kprintf("AHCI: Version %d.%d, Ports: 0x%08x\n",
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vers >> 16, vers & 0xFFFF, ports);
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if (ports > ((1 << AHCI_MAX_PORTS) - 1))
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{
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kprintf("AHCI: Currently only supports %d ports\n", AHCI_MAX_PORTS);
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}
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int p;
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for (p = 0; p < AHCI_MAX_PORTS; p++)
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{
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if (ports & (1 << p))
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{
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ahci.port[p] = dev.bars[AHCI_ABAR].base +
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ahci->port[p] = dev.bars[AHCI_ABAR].base +
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AHCI_PORT_OFFSET + AHCI_PORT_LENGTH * p;
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} else {
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ahci.port[p] = 0;
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ahci->port[p] = 0;
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}
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}
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// Allocate memory and setup pointers
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for (p = 0; p < AHCI_MAX_PORTS; p++)
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{
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volatile AHCIPort *port = ahci->port[p];
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if (port != 0) {
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int c;
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for (c = 0; c < AHCI_MAX_CMDS; c++)
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{
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ahci->ctbl[p][c] = (AHCICommandTable *)PAlloc_AllocPage();
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memset(ahci->ctbl[p][c], 0, sizeof(AHCICommandTable));
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// XXX: VA2PA
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ahci->clst[p]->cmds[c].ctba = ahci->ctbl[p][c];
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}
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ahci->clst[p] = (AHCICommandList *)PAlloc_AllocPage();
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memset(ahci->clst[p], 0, sizeof(AHCICommandList));
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// XXX: VA2PA
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port->clba = ahci->clst[p];
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ahci->rfis[p] = (AHCIRecvFIS *)PAlloc_AllocPage();
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memset(ahci->rfis[p], 0, sizeof(AHCIRecvFIS));
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// XXX: VA2PA
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port->fb = ahci->rfis[p];
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}
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}
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// Reset controller and ports
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AHCI_Reset(ahci);
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}
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20
sys/include/sga.h
Normal file
20
sys/include/sga.h
Normal file
@ -0,0 +1,20 @@
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#ifndef __SGA_H__
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#define __SGA_H__
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#define SGARRAY_MAX_ENTRIES 32
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typedef struct SGEntry
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{
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uint64_t offset;
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uint64_t length;
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} SGEntry;
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typedef struct SGArray
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{
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uint32_t len;
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SGEntry entries[SGARRAY_MAX_ENTRIES];
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} SGArray;
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#endif /* __SGA_H__ */
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