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Add more trap, register and instruction definitions.

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This commit is contained in:
Ali Mashtizadeh 2023-11-07 12:44:54 -05:00
parent ae669bfa83
commit 9ae771481b
3 changed files with 34 additions and 33 deletions
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12
sys/arm64/include/cpu.h
View File

@ -40,6 +40,18 @@ typedef struct PageTable {
PageEntry entries[PAGETABLE_ENTRIES];
} PageTable;
/* SCTLR_EL1 */
#define SCTLR_M 0x00000001 /* MMU Enable */
#define SCTLR_A 0x00000002 /* Alignment Check */
#define SCTLR_C 0x00000004 /* Data Cache Enable */
#define SCTLR_I 0x00001000 /* Instruction Cache Enable */
#define SCTLR_UCT 0x00008000 /* CTR_EL0 Enable */
#define SCTLR_nTWI 0x00010000 /* Trap WFI Enable */
#define SCTLR_nTWE 0x00040000 /* Trap WFE Enable */
#define SCTLR_WXN 0x00080000 /* W^X Enable */
#define SCTLR_E0E 0x01000000 /* Big Endian EL0 */
#define SCTLR_EE 0x02000000 /* Big Endian EL1 */
#include "cpuop.h"
#endif /* __AMD64_H__ */

4
sys/arm64/include/cpuop.h
View File

@ -18,12 +18,12 @@ static INLINE void disable_interrupts()
static INLINE void hlt()
{
asm volatile("");
asm volatile("wfi");
}
static INLINE void pause()
{
asm volatile("");
asm volatile("yield");
}
static INLINE void breakpoint()

51
sys/arm64/include/trap.h
View File

@ -2,44 +2,33 @@
#ifndef __TRAP_H__
#define __TRAP_H__
#define T_DE 0 /* Divide Error Exception */
#define T_DB 1 /* Debug Exception */
#define T_NMI 2 /* NMI Interrupt */
#define T_BP 3 /* Breakpoint Exception */
#define T_OF 4 /* Overflow Exception */
#define T_BR 5 /* BOUND Range Exceeded Exception */
#define T_UD 6 /* Invalid Opcode Exception */
#define T_NM 7 /* Device Not Available Exception */
#define T_DF 8 /* Double Fault Exception */
#define T_TS 10 /* Invalid TSS Exception */
#define T_NP 11 /* Segment Not Present */
#define T_SS 12 /* Stack Fault Exception */
#define T_GP 13 /* General Protection Exception */
#define T_PF 14 /* Page-Fault Exception */
#define T_MF 16 /* x87 FPU Floating-Point Error */
#define T_AC 17 /* Alignment Check Exception */
#define T_MC 18 /* Machine-Check Exception */
#define T_XF 19 /* SIMB Floating-Point Exception */
#define T_VE 20 /* Virtualization Exception */
#define T_UNKNOWN 0x00 /* Unknown */
#define T_WFIWFE 0x01 /* WFI/WFE */
#define T_SIMDFP 0x07
#define T_ILLSTATE 0x0e /* Illegal Execution State */
#define T_SYSINST 0x18 /* System Instruction */
#define T_INSTABRT_L 0x20 /* Instruction Abort (EL0) */
#define T_INSTABRT 0x21 /* Instruction Abort */
#define T_PCAC 0x22 /* PC Alignment Check */
#define T_SPAC 0x26 /* SP Alignment Check */
#define T_DATAABRT_L 0x24 /* Data Abort (EL0) */
#define T_DATAABRT_L 0x25 /* Data Abort (EL0) */
#define T_SERROR 0x2f /* SError */
#define T_DBGBRK_EL0 0x32 /* Breakpoint (EL0) */
#define T_DBGBRK_EL1 0x33 /* Breakpoint (EL1) */
#define T_DBGSTP_EL0 0x32 /* Step (EL0) */
#define T_DBGSTP_EL1 0x33 /* Step (EL1) */
#define T_DBGWP_EL0 0x34 /* Watchpoint (EL0) */
#define T_DBGWP_EL1 0x35 /* Watchpoint (EL1) */
#define T_BRK 0x3c /* Breakpoint */
#define T_CPU_LAST T_VE
#define T_CPU_LAST T_BRK
// IRQs
#define T_IRQ_BASE 32
#define T_IRQ_LEN 24
#define T_IRQ_MAX (T_IRQ_BASE + T_IRQ_LEN - 1)
#define T_IRQ_TIMER (T_IRQ_BASE + 0)
#define T_IRQ_KBD (T_IRQ_BASE + 1)
#define T_IRQ_COM1 (T_IRQ_BASE + 4)
#define T_IRQ_MOUSE (T_IRQ_BASE + 12)
// LAPIC Special Vectors
#define T_IRQ_SPURIOUS (T_IRQ_BASE + 24)
#define T_IRQ_ERROR (T_IRQ_BASE + 25)
#define T_IRQ_THERMAL (T_IRQ_BASE + 26)
#define T_SYSCALL 60 /* System Call */
#define T_CROSSCALL 61 /* Cross Call (IPI) */
#define T_DEBUGIPI 62 /* Kernel Debugger Halt (IPI) */