Splitting up PCI code into platform dependent parts
This commit is contained in:
Ali Mashtizadeh
parent
162c27767e
commit
c6e56a25f6
@ -20,6 +20,7 @@ src_amd64 = [
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"amd64/ioapic.c",
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"dev/x86/vgacons.c",
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"dev/ahci.c",
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"dev/pci.c",
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]
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src_common = [
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258
sys/amd64/pci.c
258
sys/amd64/pci.c
@ -7,16 +7,6 @@
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#include "amd64.h"
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#include "amd64op.h"
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void PCI_ScanBus();
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void
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PCI_Init()
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{
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kprintf("Initializing PCI\n");
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PCI_ScanBus();
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kprintf("PCI Initialization Done\n");
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}
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#define PCI_PORT_ADDR 0xCF8
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#define PCI_PORT_DATABASE 0xCFC
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@ -94,251 +84,3 @@ PCICfgWrite32(uint32_t bus, uint32_t slot, uint32_t func, uint32_t reg,
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outl(port, data);
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}
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uint16_t
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PCIGetDeviceID(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead16(bus, device, func, PCI_OFFSET_DEVICEID);
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}
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uint16_t
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PCIGetVendorID(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead16(bus, device, func, PCI_OFFSET_VENDORID);
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}
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uint8_t
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PCIGetBaseClass(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead8(bus, device, func, PCI_OFFSET_CLASS);
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}
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uint8_t
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PCIGetSubClass(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead8(bus, device, func, PCI_OFFSET_SUBCLASS);
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}
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uint8_t
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PCIGetHeaderType(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead8(bus, device, func, PCI_OFFSET_HEADERTYPE);
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}
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uint8_t
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PCI_CfgRead8(PCIDevice *dev, uint32_t reg)
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{
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return PCICfgRead8(dev->bus, dev->slot, dev->func, reg);
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}
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uint16_t
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PCI_CfgRead16(PCIDevice *dev, uint32_t reg)
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{
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return PCICfgRead16(dev->bus, dev->slot, dev->func, reg);
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}
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uint32_t
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PCI_CfgRead32(PCIDevice *dev, uint32_t reg)
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{
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return PCICfgRead32(dev->bus, dev->slot, dev->func, reg);
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}
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void
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PCI_CfgWrite8(PCIDevice *dev, uint32_t reg, uint8_t data)
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{
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return PCICfgWrite8(dev->bus, dev->slot, dev->func, reg, data);
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}
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void
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PCI_CfgWrite16(PCIDevice *dev, uint32_t reg, uint16_t data)
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{
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return PCICfgWrite16(dev->bus, dev->slot, dev->func, reg, data);
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}
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void
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PCI_CfgWrite32(PCIDevice *dev, uint32_t reg, uint32_t data)
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{
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return PCICfgWrite32(dev->bus, dev->slot, dev->func, reg, data);
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}
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uint16_t
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PCI_GetDeviceID(PCIDevice *dev)
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{
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return PCI_CfgRead16(dev, PCI_OFFSET_DEVICEID);
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}
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uint16_t
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PCI_GetVendorID(PCIDevice *dev)
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{
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return PCI_CfgRead16(dev, PCI_OFFSET_VENDORID);
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}
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uint8_t
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PCI_GetBaseClass(PCIDevice *dev)
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{
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return PCI_CfgRead8(dev, PCI_OFFSET_CLASS);
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}
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uint8_t
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PCI_GetSubClass(PCIDevice *dev)
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{
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return PCI_CfgRead8(dev, PCI_OFFSET_SUBCLASS);
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}
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uint8_t
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PCI_GetHeaderType(PCIDevice *dev)
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{
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return PCI_CfgRead8(dev, PCI_OFFSET_HEADERTYPE);
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}
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void
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PCICheckFunction(uint32_t bus, uint32_t device, uint32_t func)
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{
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uint8_t baseClass, subClass;
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uint16_t vendorId, deviceId;
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baseClass = PCIGetBaseClass(bus, device, func);
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subClass = PCIGetSubClass(bus, device, func);
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vendorId = PCIGetVendorID(bus, device, func);
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deviceId = PCIGetDeviceID(bus, device, func);
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if (baseClass == PCI_CLASS_BRIDGE) {
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if (subClass == PCI_SCLASS_BRIDGE_HOST) {
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kprintf("PCI(%d,%d,%d): Host Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if (subClass == PCI_SCLASS_BRIDGE_ISA) {
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kprintf("PCI(%d,%d,%d): ISA Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if (subClass == PCI_SCLASS_BRIDGE_PCI) {
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kprintf("PCI(%d,%d,%d): PCI-PCI Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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// Scan sub-bus
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} else if (subClass == PCI_SCLASS_BRIDGE_MISC) {
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kprintf("PCI(%d,%d,%d): Other Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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}
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} else if (baseClass == PCI_CLASS_STORAGE) {
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if (subClass == PCI_SCLASS_STORAGE_SATA) {
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kprintf("PCI(%d,%d,%d): SATA Controller (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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AHCI_Init(bus, device, func);
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} else if (subClass == PCI_SCLASS_STORAGE_IDE) {
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kprintf("PCI(%d,%d,%d): IDE Controller (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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}
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} else if ((baseClass == PCI_CLASS_NETWORK) && (subClass == 0x00)) {
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kprintf("PCI(%d,%d,%d): Ethernet (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if ((baseClass == PCI_CLASS_GRAPHICS) && (subClass == 0x00)) {
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kprintf("PCI(%d,%d,%d): VGA (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if ((baseClass == PCI_CLASS_BUS) && (subClass == PCI_SCLASS_BUS_SMBUS)) {
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kprintf("PCI(%d,%d,%d): SMBUS (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else {
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kprintf("PCI(%d,%d,%d): Unsupported (%04x:%04x %02x:%02x)\n",
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bus, device, func, vendorId, deviceId, baseClass, subClass);
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}
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}
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void
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PCIScanDevice(uint32_t bus, uint32_t device)
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{
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uint8_t headerType;
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uint16_t vendorId;
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vendorId = PCIGetVendorID(bus, device, 0);
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if (vendorId == 0xFFFF)
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return;
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PCICheckFunction(bus, device, 0);
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headerType = PCIGetHeaderType(bus, device, 0);
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if ((headerType & 0x80) != 0) {
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uint8_t func;
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for (func = 0; func < 8; func++) {
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if (PCIGetVendorID(bus, device, func) != 0xFFFF) {
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PCICheckFunction(bus, device, func);
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}
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}
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}
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}
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void
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PCIScanBus(uint8_t bus)
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{
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uint8_t device;
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for (device = 0; device < 32; device++) {
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PCIScanDevice(bus, device);
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}
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}
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void
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PCI_ScanBus()
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{
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uint8_t headerType = PCIGetHeaderType(0, 0, 0);
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if ((headerType & 0x80) == 0) {
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PCIScanBus(0);
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} else {
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uint8_t busNo;
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for (busNo = 0; busNo < 8; busNo++) {
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if (PCIGetVendorID(0, 0, busNo) != 0xFFFF)
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break;
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PCIScanBus(busNo);
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}
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}
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}
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void
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PCI_Configure(PCIDevice *dev)
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{
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int bar;
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dev->irq = PCI_CfgRead8(dev, PCI_OFFSET_IRQLINE);
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PCI_CfgWrite16(dev, PCI_OFFSET_COMMAND,
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PCI_COMMAND_IOENABLE | PCI_COMMAND_MEMENABLE | PCI_COMMAND_BUSMASTER);
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for (bar = 0; bar < PCI_MAX_BARS; bar++)
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{
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dev->bars[bar].base = 0;
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dev->bars[bar].size = 0;
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dev->bars[bar].type = PCIBAR_TYPE_NULL;
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}
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for (bar = 0; bar < PCI_MAX_BARS; bar++)
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{
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uint32_t barReg = PCI_OFFSET_BARFIRST + 4 * bar;
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uint32_t base, size;
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uint32_t origValue = PCI_CfgRead32(dev, barReg);
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PCI_CfgWrite32(dev, barReg, 0xFFFFFFFF);
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size = PCI_CfgRead32(dev, barReg);
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if (size == 0)
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continue;
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PCI_CfgWrite32(dev, barReg, origValue);
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if (origValue & 0x1)
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{
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dev->bars[bar].type = PCIBAR_TYPE_IO;
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base = origValue & 0xFFFFFFFC;
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size = size & 0xFFFFFFFC;
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size = ~size + 1;
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} else {
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dev->bars[bar].type = PCIBAR_TYPE_MEM;
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base = origValue & 0xFFFFFFF0;
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size = size & 0xFFFFFFF0;
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size = ~size + 1;
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// XXX: Support 64-bit
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ASSERT((origValue & 0x06) == 0x00);
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}
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dev->bars[bar].base = base;
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dev->bars[bar].size = size;
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}
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}
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264
sys/dev/pci.c
Normal file
264
sys/dev/pci.c
Normal file
@ -0,0 +1,264 @@
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#include <stdint.h>
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#include <kassert.h>
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#include <pci.h>
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void PCI_ScanBus();
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void
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PCI_Init()
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{
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kprintf("Initializing PCI\n");
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PCI_ScanBus();
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kprintf("PCI Initialization Done\n");
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}
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uint16_t
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PCIGetDeviceID(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead16(bus, device, func, PCI_OFFSET_DEVICEID);
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}
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uint16_t
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PCIGetVendorID(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead16(bus, device, func, PCI_OFFSET_VENDORID);
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}
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uint8_t
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PCIGetBaseClass(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead8(bus, device, func, PCI_OFFSET_CLASS);
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}
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uint8_t
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PCIGetSubClass(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead8(bus, device, func, PCI_OFFSET_SUBCLASS);
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}
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uint8_t
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PCIGetHeaderType(uint32_t bus, uint32_t device, uint32_t func)
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{
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return PCICfgRead8(bus, device, func, PCI_OFFSET_HEADERTYPE);
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}
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uint8_t
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PCI_CfgRead8(PCIDevice *dev, uint32_t reg)
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{
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return PCICfgRead8(dev->bus, dev->slot, dev->func, reg);
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}
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uint16_t
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PCI_CfgRead16(PCIDevice *dev, uint32_t reg)
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{
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return PCICfgRead16(dev->bus, dev->slot, dev->func, reg);
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}
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uint32_t
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PCI_CfgRead32(PCIDevice *dev, uint32_t reg)
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{
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return PCICfgRead32(dev->bus, dev->slot, dev->func, reg);
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}
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void
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PCI_CfgWrite8(PCIDevice *dev, uint32_t reg, uint8_t data)
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{
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return PCICfgWrite8(dev->bus, dev->slot, dev->func, reg, data);
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}
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void
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PCI_CfgWrite16(PCIDevice *dev, uint32_t reg, uint16_t data)
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{
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return PCICfgWrite16(dev->bus, dev->slot, dev->func, reg, data);
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}
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void
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PCI_CfgWrite32(PCIDevice *dev, uint32_t reg, uint32_t data)
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{
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return PCICfgWrite32(dev->bus, dev->slot, dev->func, reg, data);
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}
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uint16_t
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PCI_GetDeviceID(PCIDevice *dev)
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{
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return PCI_CfgRead16(dev, PCI_OFFSET_DEVICEID);
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}
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uint16_t
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PCI_GetVendorID(PCIDevice *dev)
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{
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return PCI_CfgRead16(dev, PCI_OFFSET_VENDORID);
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}
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uint8_t
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PCI_GetBaseClass(PCIDevice *dev)
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{
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return PCI_CfgRead8(dev, PCI_OFFSET_CLASS);
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}
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uint8_t
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PCI_GetSubClass(PCIDevice *dev)
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{
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return PCI_CfgRead8(dev, PCI_OFFSET_SUBCLASS);
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}
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uint8_t
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PCI_GetHeaderType(PCIDevice *dev)
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{
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return PCI_CfgRead8(dev, PCI_OFFSET_HEADERTYPE);
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}
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void
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PCICheckFunction(uint32_t bus, uint32_t device, uint32_t func)
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{
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uint8_t baseClass, subClass;
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uint16_t vendorId, deviceId;
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baseClass = PCIGetBaseClass(bus, device, func);
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subClass = PCIGetSubClass(bus, device, func);
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vendorId = PCIGetVendorID(bus, device, func);
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deviceId = PCIGetDeviceID(bus, device, func);
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if (baseClass == PCI_CLASS_BRIDGE) {
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if (subClass == PCI_SCLASS_BRIDGE_HOST) {
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kprintf("PCI(%d,%d,%d): Host Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if (subClass == PCI_SCLASS_BRIDGE_ISA) {
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kprintf("PCI(%d,%d,%d): ISA Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if (subClass == PCI_SCLASS_BRIDGE_PCI) {
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kprintf("PCI(%d,%d,%d): PCI-PCI Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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// Scan sub-bus
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} else if (subClass == PCI_SCLASS_BRIDGE_MISC) {
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kprintf("PCI(%d,%d,%d): Other Bridge (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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}
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} else if (baseClass == PCI_CLASS_STORAGE) {
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if (subClass == PCI_SCLASS_STORAGE_SATA) {
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kprintf("PCI(%d,%d,%d): SATA Controller (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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AHCI_Init(bus, device, func);
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} else if (subClass == PCI_SCLASS_STORAGE_IDE) {
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kprintf("PCI(%d,%d,%d): IDE Controller (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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}
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} else if ((baseClass == PCI_CLASS_NETWORK) && (subClass == 0x00)) {
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kprintf("PCI(%d,%d,%d): Ethernet (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if ((baseClass == PCI_CLASS_GRAPHICS) && (subClass == 0x00)) {
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kprintf("PCI(%d,%d,%d): VGA (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else if ((baseClass == PCI_CLASS_BUS) && (subClass == PCI_SCLASS_BUS_SMBUS)) {
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kprintf("PCI(%d,%d,%d): SMBUS (%04x:%04x)\n",
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bus, device, func, vendorId, deviceId);
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} else {
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kprintf("PCI(%d,%d,%d): Unsupported (%04x:%04x %02x:%02x)\n",
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bus, device, func, vendorId, deviceId, baseClass, subClass);
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}
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}
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void
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PCIScanDevice(uint32_t bus, uint32_t device)
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{
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uint8_t headerType;
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uint16_t vendorId;
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vendorId = PCIGetVendorID(bus, device, 0);
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if (vendorId == 0xFFFF)
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return;
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PCICheckFunction(bus, device, 0);
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headerType = PCIGetHeaderType(bus, device, 0);
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if ((headerType & 0x80) != 0) {
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uint8_t func;
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for (func = 0; func < 8; func++) {
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if (PCIGetVendorID(bus, device, func) != 0xFFFF) {
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PCICheckFunction(bus, device, func);
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}
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}
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}
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}
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void
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PCIScanBus(uint8_t bus)
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{
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uint8_t device;
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|
||||
for (device = 0; device < 32; device++) {
|
||||
PCIScanDevice(bus, device);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
PCI_ScanBus()
|
||||
{
|
||||
uint8_t headerType = PCIGetHeaderType(0, 0, 0);
|
||||
|
||||
if ((headerType & 0x80) == 0) {
|
||||
PCIScanBus(0);
|
||||
} else {
|
||||
uint8_t busNo;
|
||||
|
||||
for (busNo = 0; busNo < 8; busNo++) {
|
||||
if (PCIGetVendorID(0, 0, busNo) != 0xFFFF)
|
||||
break;
|
||||
PCIScanBus(busNo);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
PCI_Configure(PCIDevice *dev)
|
||||
{
|
||||
int bar;
|
||||
|
||||
dev->irq = PCI_CfgRead8(dev, PCI_OFFSET_IRQLINE);
|
||||
|
||||
PCI_CfgWrite16(dev, PCI_OFFSET_COMMAND,
|
||||
PCI_COMMAND_IOENABLE | PCI_COMMAND_MEMENABLE | PCI_COMMAND_BUSMASTER);
|
||||
|
||||
for (bar = 0; bar < PCI_MAX_BARS; bar++)
|
||||
{
|
||||
dev->bars[bar].base = 0;
|
||||
dev->bars[bar].size = 0;
|
||||
dev->bars[bar].type = PCIBAR_TYPE_NULL;
|
||||
}
|
||||
|
||||
for (bar = 0; bar < PCI_MAX_BARS; bar++)
|
||||
{
|
||||
uint32_t barReg = PCI_OFFSET_BARFIRST + 4 * bar;
|
||||
uint32_t base, size;
|
||||
uint32_t origValue = PCI_CfgRead32(dev, barReg);
|
||||
|
||||
PCI_CfgWrite32(dev, barReg, 0xFFFFFFFF);
|
||||
size = PCI_CfgRead32(dev, barReg);
|
||||
if (size == 0)
|
||||
continue;
|
||||
|
||||
PCI_CfgWrite32(dev, barReg, origValue);
|
||||
|
||||
if (origValue & 0x1)
|
||||
{
|
||||
dev->bars[bar].type = PCIBAR_TYPE_IO;
|
||||
base = origValue & 0xFFFFFFFC;
|
||||
size = size & 0xFFFFFFFC;
|
||||
size = ~size + 1;
|
||||
} else {
|
||||
dev->bars[bar].type = PCIBAR_TYPE_MEM;
|
||||
base = origValue & 0xFFFFFFF0;
|
||||
size = size & 0xFFFFFFF0;
|
||||
size = ~size + 1;
|
||||
// XXX: Support 64-bit
|
||||
ASSERT((origValue & 0x06) == 0x00);
|
||||
}
|
||||
|
||||
dev->bars[bar].base = base;
|
||||
dev->bars[bar].size = size;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user