Improvements to AHCI driver and part of a IDE PIO driver.
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696101f277
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@ -18,8 +18,9 @@ src_amd64 = [
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"amd64/pmap.c",
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"amd64/lapic.c",
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"amd64/ioapic.c",
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"dev/x86/vgacons.c",
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"dev/x86/debugcons.c",
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"dev/x86/vgacons.c",
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"dev/x86/ide.c",
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]
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src_common = [
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@ -87,5 +87,6 @@ void Machine_Init()
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IOAPIC_Init();
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PCI_Init();
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IDE_Init();
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}
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@ -261,6 +261,18 @@ AHCI_Init(uint32_t bus, uint32_t slot, uint32_t func)
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}
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}
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void
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AHCI_Dump(AHCI *ahci)
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{
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volatile AHCIHostControl *hc = ahci->hc;
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kprintf("CAP: 0x%08x\n", hc->cap);
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kprintf("GHC: 0x%08x\n", hc->ghc);
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kprintf("IS: 0x%08x\n", hc->is);
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kprintf("PI: 0x%08x\n", hc->pi);
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kprintf("VS: 0x%08x\n", hc->vs);
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}
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void
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AHCI_DumpPort(AHCI *ahci, int port)
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{
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@ -351,6 +363,8 @@ AHCI_IdentifyPort(AHCI *ahci, int port)
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kprintf("AHCI: Identify Succeeded Port %d\n", port);
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Debug_PrintHex((const char *)&ident, 512, 0, 512);
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AHCI_DumpPort(ahci, port);
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uint64_t val = (uint64_t)&ident;
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Debug_PrintHex((const char *)&val, 8, 0, 8);
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return;
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}
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@ -377,6 +391,10 @@ AHCI_ResetPort(AHCI *ahci, int port)
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}
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}
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// Reset interrupts
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p->is = 0xFFFFFFFF;
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p->is = 0x00000000;
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// Reset error
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p->serr = 0xFFFFFFFF;
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p->serr = 0x00000000;
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@ -406,9 +424,23 @@ void
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AHCI_Reset(AHCI *ahci)
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{
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int port;
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volatile AHCIHostControl *hc = ahci->hc;
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// Enable AHCI and Interrupts
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ahci->hc->ghc = AHCI_GHC_AE | AHCI_GHC_IE;
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AHCI_Dump(ahci);
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// Reset controller
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uint32_t caps = hc->cap;
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uint32_t pi = hc->pi;
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hc->ghc |= AHCI_GHC_AE;
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hc->ghc |= AHCI_GHC_HR;
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while (1) {
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if ((hc->ghc & AHCI_GHC_HR) == 0)
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break;
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}
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hc->ghc |= AHCI_GHC_AE;
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AHCI_Dump(ahci);
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// Reset ports
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for (port = 0; port < AHCI_MAX_PORTS; port++)
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@ -417,12 +449,18 @@ AHCI_Reset(AHCI *ahci)
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AHCI_ResetPort(ahci, port);
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}
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}
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// XXX: Clear interrupts
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// Enable Interrupts
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hc->ghc = AHCI_GHC_IE;
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}
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void
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AHCI_Configure(PCIDevice dev)
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{
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AHCI *ahci = (AHCI *)PAlloc_AllocPage();
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volatile AHCIHostControl *hc;
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PCI_Configure(&dev);
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@ -445,10 +483,17 @@ AHCI_Configure(PCIDevice dev)
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// XXX: Register IRQ
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// Setup
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ahci->hc = dev.bars[AHCI_ABAR].base;
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hc = dev.bars[AHCI_ABAR].base;
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ahci->hc = hc;
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uint32_t ports = ahci->hc->pi;
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uint32_t vers = ahci->hc->vs;
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// Disable Interrupts
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hc->ghc &= ~AHCI_GHC_IE;
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// Enable AHCI Controller
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hc->ghc |= AHCI_GHC_AE;
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uint32_t ports = hc->pi;
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uint32_t vers = hc->vs;
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kprintf("AHCI: Version %d.%d, Ports: 0x%08x\n",
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vers >> 16, vers & 0xFFFF, ports);
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190
sys/dev/x86/ide.c
Normal file
190
sys/dev/x86/ide.c
Normal file
@ -0,0 +1,190 @@
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#include <stdbool.h>
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#include <stdint.h>
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#include <kassert.h>
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#include <sga.h>
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#include "ioport.h"
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/*
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* ATA Definitions
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*/
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typedef struct ATAIdentifyDevice
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{
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uint16_t _rsvd0[10]; // 0-9
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uint8_t serial[20]; // 10-19 - Serial
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uint16_t _rsvd1[3]; // 20-22
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uint8_t firmware[8]; // 23-26 - Firmware
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uint8_t model[40]; // 27-46 - Model
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uint16_t _rsvd2[16]; // 47-62 X
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uint16_t dmaMode; // 63 - DMA Mode
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uint16_t _rsvd3[11]; // 64-74 X
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uint16_t queueDepth; // 75 - Queue Depth
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uint16_t sataCap; // 76 - SATA Capabilities
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uint16_t ncqCap; // 77 - NCQ Capabilities
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uint16_t _rsvd4[8]; // 78-85
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uint16_t deviceFlags; // 86 - Device Flags (48-bit Addressing)
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uint16_t deviceFlags2; // 87 - Device Flags 2 (SMART)
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uint16_t udmaMode; // 88 - Ultra DMA Mode
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uint16_t _rsvd5[11]; // 89-99
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uint64_t lbaSectors; // 100-103 - User Addressable Logical Sectors
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uint16_t _rsvd6[151]; // 104-254
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uint16_t chksum; // 255 - Checksum
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} ATAIdentifyDevice;
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/*
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* IDE Definitions
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*/
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#define IDE_PRIMARY_BASE 0x1F0
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#define IDE_PRIMARY_DEVCTL 0x3F6
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#define IDE_PRIMARY_IRQ 14
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#define IDE_SECONDARY_BASE 0x170
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#define IDE_SECONDARY_DEVCTL 0x376
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#define IDE_SECONDARY_IRQ 15
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// Port Offsets
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#define IDE_DATAPORT 0
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#define IDE_FEATURES 1
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#define IDE_SECTORCOUNT 2
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#define IDE_LBALOW 3
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#define IDE_LBAMID 4
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#define IDE_LBAHIGH 5
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#define IDE_DRIVE 6
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#define IDE_COMMAND 7 /* Write */
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#define IDE_STATUS 7 /* Read */
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// Drives
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#define IDE_DRIVE_MASTER 0xA0
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#define IDE_DRIVE_SLAVE 0xB0
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// IDE Commands
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#define IDE_CMD_READ
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#define IDE_CMD_WRITE
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#define IDE_CMD_IDENTIFY 0xEC
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// Status
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#define IDE_STATUS_ERR 0x01 /* Error */
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#define IDE_STATUS_DRQ 0x08 /* Data Ready */
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#define IDE_STATUS_SRV 0x10 /* Overlapped-mode Service Request */
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#define IDE_STATUS_DF 0x20 /* Drive Fault Error */
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#define IDE_STATUS_RDY 0x40 /* Ready */
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#define IDE_STATUS_BSY 0x80 /* Busy */
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#define IDE_CONTROL_SRST 0x04 /* Software Reset */
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typedef struct IDE
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{
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uint16_t base; // Base Port
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uint16_t devctl; // Device Control
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} IDE;
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bool IDE_HasController(IDE *ide);
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void IDE_Reset(IDE *ide);
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void IDE_Identify(IDE *ide, int drive);
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void
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IDE_Init()
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{
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IDE ide;
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ASSERT(sizeof(ATAIdentifyDevice) == 512);
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ide.base = IDE_PRIMARY_BASE;
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ide.devctl = IDE_PRIMARY_DEVCTL;
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if (!IDE_HasController(&ide)) {
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kprintf("IDE: No controller detected\n");
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return;
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}
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IDE_Reset(&ide);
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IDE_Identify(&ide, 0);
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}
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bool
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IDE_HasController(IDE *ide)
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{
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outb(ide->base + IDE_LBALOW, 0x41);
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outb(ide->base + IDE_LBAMID, 0x4D);
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if (inb(ide->base + IDE_LBALOW) != 0x41)
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return false;
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if (inb(ide->base + IDE_LBAMID) != 0x4D)
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return false;
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return true;
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}
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void
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IDE_Reset(IDE *ide)
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{
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uint8_t status;
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outb(ide->devctl, IDE_CONTROL_SRST);
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outb(ide->devctl, 0);
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inb(ide->devctl);
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inb(ide->devctl);
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inb(ide->devctl);
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inb(ide->devctl);
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// XXX: Timeout
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while (1) {
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status = inb(ide->devctl);
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if ((status & (IDE_STATUS_RDY | IDE_STATUS_BSY)) == IDE_STATUS_RDY)
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break;
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}
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}
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void
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IDE_Identify(IDE *ide, int drive)
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{
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uint8_t driveCode;
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uint8_t status;
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ATAIdentifyDevice ident;
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ASSERT(drive == 0 || drive == 1);
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if (drive == 0)
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driveCode = IDE_DRIVE_MASTER;
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else
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driveCode = IDE_DRIVE_SLAVE;
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outb(ide->base + IDE_DRIVE, driveCode);
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outb(ide->base + IDE_SECTORCOUNT, 0x00);
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outb(ide->base + IDE_LBALOW, 0x00);
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outb(ide->base + IDE_LBAMID, 0x00);
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outb(ide->base + IDE_LBAHIGH, 0x00);
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outb(ide->base + IDE_COMMAND, IDE_CMD_IDENTIFY);
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status = inb(ide->base + IDE_STATUS);
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if (status == 0) {
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kprintf("IDE: No drive %d\n", drive);
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return;
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}
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kprintf("IDE: Waiting for ready! %08x\n", status);
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// XXX: Need timeout
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while (1) {
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if ((status & IDE_STATUS_BSY) == 0)
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break;
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status = inb(ide->base + IDE_STATUS);
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}
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if ((status & IDE_STATUS_ERR) != 0) {
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kprintf("IDE: Error trying to identify drive %d\n", drive);
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return;
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}
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kprintf("IDE: Ready!\n");
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insw(ide->base, (void *)&ident, 256);
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kprintf("IDE: Ready!\n");
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Debug_PrintHex((const char *)&ident, 512, 0, 512);
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}
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