193 lines
4.9 KiB
C
193 lines
4.9 KiB
C
/*
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* Copyright (c) 2013-2014 Stanford University
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* All rights reserved.
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*/
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#ifndef __AMD64_H__
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#define __AMD64_H__
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/*
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* Page Tables
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*/
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#define PGIDXSHIFT 9
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#define PGIDXMASK (512 - 1)
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#define PGSHIFT 12
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#define PGSIZE (1 << PGSHIFT)
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#define PGMASK (PGSIZE - 1)
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#define LARGE_PGSHIFT 21
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#define LARGE_PGSIZE (1 << LARGE_PGSHIFT)
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#define LARGE_PGMASK (LARGE_PGSIZE - 1)
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#define HUGE_PGSHIFT 30
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#define HUGE_PGSIZE (1 << HUGE_PGSHIFT)
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#define HUGE_PGMASK (HUGE_PGSIZE - 1)
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#define ROUNDUP_PGSIZE(x) (((x) + LARGE_PGSIZE - 1) & ~LARGE_PGMASK)
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#define ROUNDDOWN_PGSIZE(x) ((x) & ~LARGE_PGMASK)
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#define PTE_P 0x0001 /* Present */
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#define PTE_W 0x0002 /* Writeable */
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#define PTE_U 0x0004 /* User */
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#define PTE_PWT 0x0008 /* Write Through */
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#define PTE_PCD 0x0010 /* Cache Disable */
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#define PTE_A 0x0020 /* Accessed */
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#define PTE_D 0x0040 /* Dirty */
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#define PTE_PS 0x0080 /* Page Size */
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#define PTE_G 0x0100 /* Global */
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#define PTE_OS1 0x0200 /* Available */
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#define PTE_OS2 0x0400 /* Available */
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#define PTE_OS3 0x0800 /* Available */
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#define PTE_PAT 0x1000 /* Page Attribute Table */
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#define PTE_NX 0x8000000000000000ULL /* No Execute */
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#define PAGETABLE_ENTRIES 512
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typedef uint64_t PageEntry;
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typedef struct PageTable {
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PageEntry entries[PAGETABLE_ENTRIES];
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} PageTable;
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/*
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* Global Descriptor Table
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*/
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typedef struct PACKED PseudoDescriptor {
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uint16_t lim;
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uint64_t off;
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} PseudoDescriptor;
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#define SEG_G
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#define SEG_DB
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#define SEG_L
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#define SEG_P
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#define SEG_DPL_SHIFT 45
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#define SEG_S
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#define SEG_CS (0xE << 40)
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#define SEG_DS (0x2 << 40)
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#define SEG_TSA (0x9 << 40)
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#define SEG_TSB (0xB << 40)
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#define SEL_KCS 0x08
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#define SEL_KDS 0x10
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#define SEL_TSS 0x20
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#define SEL_UCS 0x28
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#define SEL_UDS 0x30
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typedef uint64_t SegmentDescriptor;
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/*
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* Interrupt Descriptor Table
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*/
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typedef struct PACKED InteruptGate64 {
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uint16_t pc_low;
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uint16_t cs;
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uint8_t ist;
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uint8_t type;
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uint16_t pc_mid;
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uint32_t pc_high;
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uint32_t _unused1;
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} InteruptGate64;
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/*
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* Task State Segment
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*/
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typedef struct PACKED TaskStateSegment64 {
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uint16_t iomap_offset;
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uint16_t _unused0;
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uint32_t _unused1;
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uint32_t _unused2;
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uint64_t ist7;
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uint64_t ist6;
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uint64_t ist5;
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uint64_t ist4;
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uint64_t ist3;
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uint64_t ist2;
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uint64_t ist1;
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uint64_t _unused3;
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uint64_t rsp2;
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uint64_t rsp1;
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uint64_t rsp0;
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uint32_t _unused4;
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} TaskStateSegment64;
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/*
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* Control Registers
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*/
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#define CR0_PE 0x00000001 /* Protection Enabled */
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#define CR0_MP 0x00000002 /* Monitor Coprocessor */
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#define CR0_EM 0x00000004 /* Emulation */
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#define CR0_TS 0x00000008 /* Task Switched */
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#define CR0_ET 0x00000010 /* Extension Type */
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#define CR0_NE 0x00000020 /* Numeric Error */
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#define CR0_WP 0x00010000 /* Write Protect */
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#define CR0_AM 0x00040000 /* Alignment Mask */
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#define CR0_NW 0x20000000 /* Not Writethrough */
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#define CR0_CD 0x40000000 /* Cache Disable */
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#define CR0_PG 0x80000000 /* Paging */
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#define CR4_VME 0x00000001 /* Virtual 8086 Mode Enable */
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#define CR4_PVI 0x00000002 /* Protected-Mode Virtual Interupts */
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#define CR4_TSD 0x00000004 /* Time Stamp Diable */
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#define CR4_DE 0x00000008 /* Debugging Extensions */
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#define CR4_PSE 0x00000010 /* Page Size Extensions */
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#define CR4_PAE 0x00000020 /* Physical Address Extension */
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#define CR4_MCE 0x00000040 /* Machine Check Enable */
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#define CR4_PGE 0x00000080 /* Page Global Enable */
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#define CR4_PCE 0x00000100 /* Performance Monitoring Counter Enable */
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#define CR4_OSFXSR 0x00000200 /* OS FXSAVE/FXRSTOR Support */
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#define CR4_OSXMMEXCPT 0x00000400 /* OS Unmasked Exception Support */
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#define CR4_FSGSBASE 0x00010000 /* Enable FS/GS read/write Instructions */
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#define CR4_OSXSAVE 0x00040000 /* XSAVE and Processor Extended States Enable */
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#define RFLAGS_CF 0x00000001 /* Carry Flag */
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#define RFLAGS_PF 0x00000004 /* Parity Flag */
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#define RFLAGS_AF
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#define RFLAGS_ZF
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#define RFLAGS_SF
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#define RFLAGS_TF
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#define RFLAGS_IF
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#define RFLAGS_DF
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#define RFLAGS_OF
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// IOPL
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#define RFLAGS_NT
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#define RFLAGS_RF 0x00010000
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#define RFLAGS_VM 0x00020000
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#define RFLAGS_AC 0x00040000
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#define RFLAGS_VIF 0x00080000
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#define RFLAGS_VIP
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#define RFLAGS_ID
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/*
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* Debug Registers
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*/
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/*
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* MSRs
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*/
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#define MSR_EFER 0xC0000080
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#define EFER_SCE 0x0001 /* Syscall Enable */
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#define EFER_LME 0x0100 /* Long Mode Enable */
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#define EFER_LMA 0x0400 /* Long Mode Active */
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#define EFER_NXE 0x0800 /* Enable Execute Disable */
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#define EFER_SVME 0x1000 /* SVM Enable (AMD) */
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#define EFER_SLE 0x2000 /* Long Mode Segment Limit Enable (AMD) */
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#define EFER_FFXSR 0x4000 /* Fast FXSAVE/FXRSTOR (AMD) */
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#define EFER_TCE 0x8000 /* Translation Cache Extension (AMD) */
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#include "amd64op.h"
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#endif /* __AMD64_H__ */
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