metal-cos/sys/arm64/trapentry.S
2023-12-01 05:28:53 +08:00

99 lines
1.9 KiB
ArmAsm

/*
* Trap Handlers
*/
.extern trap_entry
.text
trap_locore_entry:
stp lr, lr, [sp, #-16]!
stp x28, x29, [sp, #-16]!
stp x26, x27, [sp, #-16]!
stp x24, x25, [sp, #-16]!
stp x22, x23, [sp, #-16]!
stp x20, x21, [sp, #-16]!
stp x18, x19, [sp, #-16]!
stp x16, x17, [sp, #-16]!
stp x14, x15, [sp, #-16]!
stp x12, x13, [sp, #-16]!
stp x10, x11, [sp, #-16]!
stp x8, x9, [sp, #-16]!
stp x6, x7, [sp, #-16]!
stp x4, x5, [sp, #-16]!
stp x2, x3, [sp, #-16]!
stp x0, x1, [sp, #-16]!
; mrs x0, spsr_el1
; mrs x1, elr_el1
; stp x0, x1, [sp, #-16]!
.extern trap_entry
bl trap_entry
; ldp x0, x1, [sp], #16
; msr spsr_el1, x0
; msr elr_el1, x1
ldp x0, x1, [sp], #16
ldp x2, x3, [sp], #16
ldp x4, x5, [sp], #16
ldp x6, x7, [sp], #16
ldp x8, x9, [sp], #16
ldp x10, x11, [sp], #16
ldp x12, x13, [sp], #16
ldp x14, x15, [sp], #16
ldp x16, x17, [sp], #16
ldp x18, x19, [sp], #16
ldp x20, x21, [sp], #16
ldp x22, x23, [sp], #16
ldp x24, x25, [sp], #16
ldp x26, x27, [sp], #16
ldp x28, x29, [sp], #16
ldp lr, lr, [sp], #16
// daif bits are stored in PSTATE and are automatically re-enabled by eret
eret
.global _evt
.balign 2048
_evt:
// same exception level, sp0: sync, irq, fiq, serror
b _halt
.balign 0x80
b _halt
.balign 0x80
b _halt
.balign 0x80
b _halt
// same exception level, spX: sync, irq, fiq, serror
.balign 0x80
b _halt
.balign 0x80
b trap_locore_entry
b _halt
.balign 0x80
b _halt
.balign 0x80
b _halt
// higher exception level, from aarch64: sync, irq, fiq, serror
.balign 0x80
b _halt
.balign 0x80
b _halt
.balign 0x80
b _halt
.balign 0x80
b _halt
// higher exception level, from aarch32: sync, irq, fiq, serror
.balign 0x80
b _halt
.balign 0x80
b _halt
.balign 0x80
b _halt
.balign 0x80
b _halt