99 lines
1.9 KiB
ArmAsm
99 lines
1.9 KiB
ArmAsm
/*
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* Trap Handlers
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*/
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.extern trap_entry
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.text
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trap_locore_entry:
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stp lr, lr, [sp, #-16]!
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stp x28, x29, [sp, #-16]!
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stp x26, x27, [sp, #-16]!
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stp x24, x25, [sp, #-16]!
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stp x22, x23, [sp, #-16]!
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stp x20, x21, [sp, #-16]!
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stp x18, x19, [sp, #-16]!
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stp x16, x17, [sp, #-16]!
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stp x14, x15, [sp, #-16]!
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stp x12, x13, [sp, #-16]!
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stp x10, x11, [sp, #-16]!
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stp x8, x9, [sp, #-16]!
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stp x6, x7, [sp, #-16]!
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stp x4, x5, [sp, #-16]!
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stp x2, x3, [sp, #-16]!
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stp x0, x1, [sp, #-16]!
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; mrs x0, spsr_el1
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; mrs x1, elr_el1
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; stp x0, x1, [sp, #-16]!
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.extern trap_entry
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bl trap_entry
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; ldp x0, x1, [sp], #16
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; msr spsr_el1, x0
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; msr elr_el1, x1
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ldp x0, x1, [sp], #16
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ldp x2, x3, [sp], #16
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ldp x4, x5, [sp], #16
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ldp x6, x7, [sp], #16
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ldp x8, x9, [sp], #16
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ldp x10, x11, [sp], #16
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ldp x12, x13, [sp], #16
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ldp x14, x15, [sp], #16
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ldp x16, x17, [sp], #16
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ldp x18, x19, [sp], #16
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ldp x20, x21, [sp], #16
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ldp x22, x23, [sp], #16
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ldp x24, x25, [sp], #16
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ldp x26, x27, [sp], #16
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ldp x28, x29, [sp], #16
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ldp lr, lr, [sp], #16
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// daif bits are stored in PSTATE and are automatically re-enabled by eret
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eret
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.global _evt
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.balign 2048
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_evt:
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// same exception level, sp0: sync, irq, fiq, serror
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b _halt
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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// same exception level, spX: sync, irq, fiq, serror
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.balign 0x80
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b _halt
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.balign 0x80
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b trap_locore_entry
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b _halt
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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// higher exception level, from aarch64: sync, irq, fiq, serror
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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// higher exception level, from aarch32: sync, irq, fiq, serror
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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.balign 0x80
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b _halt
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