2017-12-19 10:14:40 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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2017-04-11 13:37:08 +00:00
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*
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2022-01-03 10:01:23 +00:00
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* Copyright 2016,2021 NXP
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2017-04-11 13:37:08 +00:00
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*
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*/
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2022-07-28 15:26:27 +00:00
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#ifndef BUS_FSLMC_DRIVER_H
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#define BUS_FSLMC_DRIVER_H
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2017-04-11 13:37:08 +00:00
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/**
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* @file
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*
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* RTE FSLMC Bus Interface
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*/
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdio.h>
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#include <stdlib.h>
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#include <limits.h>
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#include <errno.h>
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#include <sys/queue.h>
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#include <stdint.h>
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#include <inttypes.h>
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2017-08-25 10:19:53 +00:00
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#include <linux/vfio.h>
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2017-04-11 13:37:08 +00:00
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2022-07-28 15:26:27 +00:00
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#include <rte_compat.h>
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2017-04-11 13:37:08 +00:00
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#include <rte_debug.h>
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#include <rte_interrupts.h>
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2022-07-28 15:26:37 +00:00
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#include <dev_driver.h>
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2017-08-25 10:19:54 +00:00
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#include <rte_tailq.h>
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2018-04-25 12:56:59 +00:00
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#include <rte_devargs.h>
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2020-10-28 12:20:10 +00:00
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#include <rte_mbuf.h>
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#include <rte_mbuf_dyn.h>
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2017-08-25 10:19:54 +00:00
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#include <fslmc_vfio.h>
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2017-04-11 13:37:08 +00:00
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2022-01-03 10:01:23 +00:00
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#include "portal/dpaa2_hw_pvt.h"
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#include "portal/dpaa2_hw_dpio.h"
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2017-08-25 10:19:50 +00:00
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#define FSLMC_OBJECT_MAX_LEN 32 /**< Length of each device on bus */
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2020-10-28 12:20:10 +00:00
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#define DPAA2_INVALID_MBUF_SEQN 0
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typedef uint32_t dpaa2_seqn_t;
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extern int dpaa2_seqn_dynfield_offset;
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/**
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* Read dpaa2 sequence number from mbuf.
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*
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* @param mbuf Structure to read from.
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* @return pointer to dpaa2 sequence number.
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*/
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2021-09-03 07:17:13 +00:00
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__rte_internal
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2020-10-28 12:20:10 +00:00
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static inline dpaa2_seqn_t *
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dpaa2_seqn(struct rte_mbuf *mbuf)
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{
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return RTE_MBUF_DYNFIELD(mbuf, dpaa2_seqn_dynfield_offset,
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dpaa2_seqn_t *);
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}
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2017-12-08 05:21:17 +00:00
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/** Device driver supports link state interrupt */
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#define RTE_DPAA2_DRV_INTR_LSC 0x0008
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2017-12-08 05:21:16 +00:00
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/** Device driver supports IOVA as VA */
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#define RTE_DPAA2_DRV_IOVA_AS_VA 0X0040
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2017-04-11 13:37:08 +00:00
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struct rte_dpaa2_driver;
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2018-04-25 12:56:59 +00:00
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#define RTE_DEV_TO_FSLMC_CONST(ptr) \
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container_of(ptr, const struct rte_dpaa2_device, device)
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2017-08-25 10:19:50 +00:00
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enum rte_dpaa2_dev_type {
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/* Devices backed by DPDK driver */
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DPAA2_ETH, /**< DPNI type device*/
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DPAA2_CRYPTO, /**< DPSECI type device */
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DPAA2_CON, /**< DPCONC type device */
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/* Devices not backed by a DPDK driver: DPIO, DPBP, DPCI, DPMCP */
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DPAA2_BPOOL, /**< DPBP type device */
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DPAA2_IO, /**< DPIO type device */
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DPAA2_CI, /**< DPCI type device */
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DPAA2_MPORTAL, /**< DPMCP type device */
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2018-05-03 16:06:05 +00:00
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DPAA2_QDMA, /**< DPDMAI type device */
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2019-01-11 12:24:52 +00:00
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DPAA2_MUX, /**< DPDMUX type device */
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2019-08-29 10:27:31 +00:00
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DPAA2_DPRTC, /**< DPRTC type device */
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2022-01-03 10:01:23 +00:00
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DPAA2_DPRC, /**< DPRC type device */
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DPAA2_MAC, /**< DPMAC type device */
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2017-08-25 10:19:50 +00:00
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/* Unknown device placeholder */
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2018-01-02 13:08:38 +00:00
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DPAA2_UNKNOWN,
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DPAA2_DEVTYPE_MAX,
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2017-08-25 10:19:50 +00:00
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};
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2017-08-25 10:19:53 +00:00
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TAILQ_HEAD(rte_dpaa2_object_list, rte_dpaa2_object);
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typedef int (*rte_dpaa2_obj_create_t)(int vdev_fd,
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struct vfio_device_info *obj_info,
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int object_id);
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/**
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* A structure describing a DPAA2 object.
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*/
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struct rte_dpaa2_object {
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TAILQ_ENTRY(rte_dpaa2_object) next; /**< Next in list. */
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const char *name; /**< Name of Object. */
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enum rte_dpaa2_dev_type dev_type; /**< Type of device */
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rte_dpaa2_obj_create_t create;
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};
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2017-04-11 13:37:08 +00:00
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/**
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* A structure describing a DPAA2 device.
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*/
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struct rte_dpaa2_device {
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TAILQ_ENTRY(rte_dpaa2_device) next; /**< Next probed DPAA2 device. */
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struct rte_device device; /**< Inherit core device */
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union {
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struct rte_eth_dev *eth_dev; /**< ethernet device */
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struct rte_cryptodev *cryptodev; /**< Crypto Device */
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2022-05-05 09:05:18 +00:00
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struct rte_dma_dev *dmadev; /**< DMA Device */
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2018-05-03 16:06:05 +00:00
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struct rte_rawdev *rawdev; /**< Raw Device */
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2017-04-11 13:37:08 +00:00
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};
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2017-08-25 10:19:50 +00:00
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enum rte_dpaa2_dev_type dev_type; /**< Device Type */
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uint16_t object_id; /**< DPAA2 Object ID */
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2022-01-03 10:01:23 +00:00
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enum rte_dpaa2_dev_type ep_dev_type; /**< Endpoint Device Type */
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uint16_t ep_object_id; /**< Endpoint DPAA2 Object ID */
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char ep_name[RTE_DEV_NAME_MAX_LEN];
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2021-10-22 20:49:32 +00:00
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struct rte_intr_handle *intr_handle; /**< Interrupt handle */
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2017-04-11 13:37:08 +00:00
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struct rte_dpaa2_driver *driver; /**< Associated driver */
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2017-08-25 10:19:50 +00:00
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char name[FSLMC_OBJECT_MAX_LEN]; /**< DPAA2 Object name*/
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2017-04-11 13:37:08 +00:00
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};
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typedef int (*rte_dpaa2_probe_t)(struct rte_dpaa2_driver *dpaa2_drv,
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struct rte_dpaa2_device *dpaa2_dev);
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typedef int (*rte_dpaa2_remove_t)(struct rte_dpaa2_device *dpaa2_dev);
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/**
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* A structure describing a DPAA2 driver.
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*/
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struct rte_dpaa2_driver {
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TAILQ_ENTRY(rte_dpaa2_driver) next; /**< Next in list. */
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struct rte_driver driver; /**< Inherit core driver. */
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uint32_t drv_flags; /**< Flags for controlling device.*/
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2017-08-25 10:19:50 +00:00
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enum rte_dpaa2_dev_type drv_type; /**< Driver Type */
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2017-04-11 13:37:08 +00:00
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rte_dpaa2_probe_t probe;
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rte_dpaa2_remove_t remove;
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};
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/**
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* Register a DPAA2 driver.
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*
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* @param driver
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* A pointer to a rte_dpaa2_driver structure describing the driver
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* to be registered.
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*/
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2020-05-15 09:47:41 +00:00
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__rte_internal
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2017-04-11 13:37:08 +00:00
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void rte_fslmc_driver_register(struct rte_dpaa2_driver *driver);
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/**
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* Unregister a DPAA2 driver.
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*
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* @param driver
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* A pointer to a rte_dpaa2_driver structure describing the driver
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* to be unregistered.
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*/
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2020-05-15 09:47:41 +00:00
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__rte_internal
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2017-04-11 13:37:08 +00:00
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void rte_fslmc_driver_unregister(struct rte_dpaa2_driver *driver);
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/** Helper for DPAA2 device registration from driver (eth, crypto) instance */
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#define RTE_PMD_REGISTER_DPAA2(nm, dpaa2_drv) \
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2018-06-18 12:32:21 +00:00
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RTE_INIT(dpaa2initfn_ ##nm) \
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2017-04-11 13:37:08 +00:00
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{\
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(dpaa2_drv).driver.name = RTE_STR(nm);\
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rte_fslmc_driver_register(&dpaa2_drv); \
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} \
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RTE_PMD_EXPORT_NAME(nm, __COUNTER__)
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2017-08-25 10:19:53 +00:00
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/**
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* Register a DPAA2 MC Object driver.
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*
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* @param mc_object
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* A pointer to a rte_dpaa_object structure describing the mc object
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* to be registered.
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*/
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2020-05-15 09:47:41 +00:00
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__rte_internal
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2017-08-25 10:19:53 +00:00
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void rte_fslmc_object_register(struct rte_dpaa2_object *object);
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2018-01-02 13:08:38 +00:00
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/**
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* Count of a particular type of DPAA2 device scanned on the bus.
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*
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* @param dev_type
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* Type of device as rte_dpaa2_dev_type enumerator
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* @return
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* >=0 for count; 0 indicates either no device of the said type scanned or
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* invalid device type.
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*/
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2020-05-15 09:47:41 +00:00
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__rte_internal
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2018-01-02 13:08:38 +00:00
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uint32_t rte_fslmc_get_device_count(enum rte_dpaa2_dev_type device_type);
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2017-08-25 10:19:53 +00:00
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/** Helper for DPAA2 object registration */
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#define RTE_PMD_REGISTER_DPAA2_OBJECT(nm, dpaa2_obj) \
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2018-06-18 12:32:21 +00:00
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RTE_INIT(dpaa2objinitfn_ ##nm) \
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2017-08-25 10:19:53 +00:00
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{\
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(dpaa2_obj).name = RTE_STR(nm);\
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rte_fslmc_object_register(&dpaa2_obj); \
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} \
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RTE_PMD_EXPORT_NAME(nm, __COUNTER__)
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2017-12-08 05:21:14 +00:00
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#ifdef __cplusplus
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}
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#endif
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2022-07-28 15:26:27 +00:00
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#endif /* BUS_FSLMC_DRIVER_H */
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