2012-09-04 13:54:00 +01:00
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/*-
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* BSD LICENSE
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2014-06-04 00:42:50 +01:00
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*
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2017-11-03 20:47:23 +08:00
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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2012-09-04 13:54:00 +01:00
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* All rights reserved.
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2014-06-04 00:42:50 +01:00
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*
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2013-09-18 12:00:00 +02:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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2012-09-04 13:54:00 +01:00
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* are met:
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2014-06-04 00:42:50 +01:00
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*
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2013-09-18 12:00:00 +02:00
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* * Redistributions of source code must retain the above copyright
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2012-09-04 13:54:00 +01:00
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* notice, this list of conditions and the following disclaimer.
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2013-09-18 12:00:00 +02:00
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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2012-09-04 13:54:00 +01:00
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* distribution.
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2013-09-18 12:00:00 +02:00
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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2012-09-04 13:54:00 +01:00
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* from this software without specific prior written permission.
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2014-06-04 00:42:50 +01:00
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*
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2013-09-18 12:00:00 +02:00
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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2012-09-04 13:54:00 +01:00
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2014-10-28 13:50:54 +01:00
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#ifndef _RTE_MEMCPY_X86_64_H_
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#define _RTE_MEMCPY_X86_64_H_
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2012-09-04 13:54:00 +01:00
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2017-11-03 20:47:23 +08:00
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/**
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* @file
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*
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* Functions for SSE/AVX/AVX2/AVX512 implementation of memcpy().
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include <string.h>
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#include <rte_vect.h>
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#include <rte_common.h>
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2012-09-04 13:54:00 +01:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2017-11-03 20:47:23 +08:00
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/**
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* Copy bytes from one location to another. The locations must not overlap.
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*
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* @note This is implemented as a macro, so it's address should not be taken
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* and care is needed as parameter expressions may be evaluated multiple times.
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*
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* @param dst
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* Pointer to the destination of the data.
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* @param src
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* Pointer to the source data.
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* @param n
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* Number of bytes to copy.
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* @return
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* Pointer to the destination data.
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*/
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static __rte_always_inline void *
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rte_memcpy(void *dst, const void *src, size_t n);
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#ifdef RTE_MACHINE_CPUFLAG_AVX512F
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2016-01-17 22:05:12 -05:00
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2017-11-03 20:47:23 +08:00
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#define ALIGNMENT_MASK 0x3F
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eal: optimize aligned memcpy on x86
This patch optimizes rte_memcpy for well aligned cases, where both
dst and src addr are aligned to maximum MOV width. It introduces a
dedicated function called rte_memcpy_aligned to handle the aligned
cases with simplified instruction stream. The existing rte_memcpy
is renamed as rte_memcpy_generic. The selection between them 2 is
done at the entry of rte_memcpy.
The existing rte_memcpy is for generic cases, it handles unaligned
copies and make store aligned, it even makes load aligned for micro
architectures like Ivy Bridge. However alignment handling comes at
a price: It adds extra load/store instructions, which can cause
complications sometime.
DPDK Vhost memcpy with Mergeable Rx Buffer feature as an example:
The copy is aligned, and remote, and there is header write along
which is also remote. In this case the memcpy instruction stream
should be simplified, to reduce extra load/store, therefore reduce
the probability of load/store buffer full caused pipeline stall, to
let the actual memcpy instructions be issued and let H/W prefetcher
goes to work as early as possible.
This patch is tested on Ivy Bridge, Haswell and Skylake, it provides
up to 20% gain for Virtio Vhost PVP traffic, with packet size ranging
from 64 to 1500 bytes.
The test can also be conducted without NIC, by setting loopback
traffic between Virtio and Vhost. For example, modify the macro
TXONLY_DEF_PACKET_LEN to the requested packet size in testpmd.h,
rebuild and start testpmd in both host and guest, then "start" on
one side and "start tx_first 32" on the other.
Signed-off-by: Zhihong Wang <zhihong.wang@intel.com>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Tested-by: Lei Yao <lei.a.yao@intel.com>
2016-12-06 20:31:06 -05:00
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2016-01-17 22:05:12 -05:00
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/**
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2017-11-03 20:47:23 +08:00
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* AVX512 implementation below
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2016-01-17 22:05:12 -05:00
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*/
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2017-11-03 20:47:23 +08:00
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/**
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* Copy 16 bytes from one location to another,
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* locations should not overlap.
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*/
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static inline void
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rte_mov16(uint8_t *dst, const uint8_t *src)
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{
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__m128i xmm0;
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xmm0 = _mm_loadu_si128((const __m128i *)src);
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_mm_storeu_si128((__m128i *)dst, xmm0);
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}
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/**
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* Copy 32 bytes from one location to another,
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* locations should not overlap.
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*/
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static inline void
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rte_mov32(uint8_t *dst, const uint8_t *src)
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{
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__m256i ymm0;
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2016-01-17 22:05:12 -05:00
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2017-11-03 20:47:23 +08:00
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ymm0 = _mm256_loadu_si256((const __m256i *)src);
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_mm256_storeu_si256((__m256i *)dst, ymm0);
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}
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/**
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* Copy 64 bytes from one location to another,
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* locations should not overlap.
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*/
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static inline void
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rte_mov64(uint8_t *dst, const uint8_t *src)
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{
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__m512i zmm0;
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zmm0 = _mm512_loadu_si512((const void *)src);
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_mm512_storeu_si512((void *)dst, zmm0);
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}
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/**
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* Copy 128 bytes from one location to another,
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* locations should not overlap.
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*/
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static inline void
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rte_mov128(uint8_t *dst, const uint8_t *src)
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{
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rte_mov64(dst + 0 * 64, src + 0 * 64);
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rte_mov64(dst + 1 * 64, src + 1 * 64);
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}
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/**
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* Copy 256 bytes from one location to another,
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* locations should not overlap.
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*/
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static inline void
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rte_mov256(uint8_t *dst, const uint8_t *src)
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{
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rte_mov64(dst + 0 * 64, src + 0 * 64);
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rte_mov64(dst + 1 * 64, src + 1 * 64);
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rte_mov64(dst + 2 * 64, src + 2 * 64);
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rte_mov64(dst + 3 * 64, src + 3 * 64);
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}
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/**
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* Copy 128-byte blocks from one location to another,
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* locations should not overlap.
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*/
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static inline void
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rte_mov128blocks(uint8_t *dst, const uint8_t *src, size_t n)
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{
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__m512i zmm0, zmm1;
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while (n >= 128) {
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zmm0 = _mm512_loadu_si512((const void *)(src + 0 * 64));
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n -= 128;
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zmm1 = _mm512_loadu_si512((const void *)(src + 1 * 64));
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src = src + 128;
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_mm512_storeu_si512((void *)(dst + 0 * 64), zmm0);
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_mm512_storeu_si512((void *)(dst + 1 * 64), zmm1);
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dst = dst + 128;
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}
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}
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/**
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* Copy 512-byte blocks from one location to another,
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* locations should not overlap.
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*/
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static inline void
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rte_mov512blocks(uint8_t *dst, const uint8_t *src, size_t n)
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{
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__m512i zmm0, zmm1, zmm2, zmm3, zmm4, zmm5, zmm6, zmm7;
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while (n >= 512) {
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zmm0 = _mm512_loadu_si512((const void *)(src + 0 * 64));
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n -= 512;
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zmm1 = _mm512_loadu_si512((const void *)(src + 1 * 64));
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zmm2 = _mm512_loadu_si512((const void *)(src + 2 * 64));
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zmm3 = _mm512_loadu_si512((const void *)(src + 3 * 64));
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zmm4 = _mm512_loadu_si512((const void *)(src + 4 * 64));
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zmm5 = _mm512_loadu_si512((const void *)(src + 5 * 64));
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zmm6 = _mm512_loadu_si512((const void *)(src + 6 * 64));
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zmm7 = _mm512_loadu_si512((const void *)(src + 7 * 64));
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src = src + 512;
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_mm512_storeu_si512((void *)(dst + 0 * 64), zmm0);
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_mm512_storeu_si512((void *)(dst + 1 * 64), zmm1);
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_mm512_storeu_si512((void *)(dst + 2 * 64), zmm2);
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_mm512_storeu_si512((void *)(dst + 3 * 64), zmm3);
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_mm512_storeu_si512((void *)(dst + 4 * 64), zmm4);
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_mm512_storeu_si512((void *)(dst + 5 * 64), zmm5);
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_mm512_storeu_si512((void *)(dst + 6 * 64), zmm6);
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_mm512_storeu_si512((void *)(dst + 7 * 64), zmm7);
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dst = dst + 512;
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}
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}
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static inline void *
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rte_memcpy_generic(void *dst, const void *src, size_t n)
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{
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uintptr_t dstu = (uintptr_t)dst;
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uintptr_t srcu = (uintptr_t)src;
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void *ret = dst;
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size_t dstofss;
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size_t bits;
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/**
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* Copy less than 16 bytes
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*/
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if (n < 16) {
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if (n & 0x01) {
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*(uint8_t *)dstu = *(const uint8_t *)srcu;
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srcu = (uintptr_t)((const uint8_t *)srcu + 1);
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dstu = (uintptr_t)((uint8_t *)dstu + 1);
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}
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if (n & 0x02) {
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*(uint16_t *)dstu = *(const uint16_t *)srcu;
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srcu = (uintptr_t)((const uint16_t *)srcu + 1);
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dstu = (uintptr_t)((uint16_t *)dstu + 1);
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}
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if (n & 0x04) {
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*(uint32_t *)dstu = *(const uint32_t *)srcu;
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srcu = (uintptr_t)((const uint32_t *)srcu + 1);
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dstu = (uintptr_t)((uint32_t *)dstu + 1);
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}
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if (n & 0x08)
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*(uint64_t *)dstu = *(const uint64_t *)srcu;
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return ret;
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}
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/**
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|
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* Fast way when copy size doesn't exceed 512 bytes
|
|
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*/
|
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if (n <= 32) {
|
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rte_mov16((uint8_t *)dst, (const uint8_t *)src);
|
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rte_mov16((uint8_t *)dst - 16 + n,
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(const uint8_t *)src - 16 + n);
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return ret;
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}
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if (n <= 64) {
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rte_mov32((uint8_t *)dst, (const uint8_t *)src);
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rte_mov32((uint8_t *)dst - 32 + n,
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(const uint8_t *)src - 32 + n);
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|
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return ret;
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|
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}
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|
|
|
if (n <= 512) {
|
|
|
|
if (n >= 256) {
|
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n -= 256;
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rte_mov256((uint8_t *)dst, (const uint8_t *)src);
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src = (const uint8_t *)src + 256;
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dst = (uint8_t *)dst + 256;
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|
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}
|
|
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|
if (n >= 128) {
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n -= 128;
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rte_mov128((uint8_t *)dst, (const uint8_t *)src);
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src = (const uint8_t *)src + 128;
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dst = (uint8_t *)dst + 128;
|
|
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}
|
|
|
|
COPY_BLOCK_128_BACK63:
|
|
|
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if (n > 64) {
|
|
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rte_mov64((uint8_t *)dst, (const uint8_t *)src);
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rte_mov64((uint8_t *)dst - 64 + n,
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|
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(const uint8_t *)src - 64 + n);
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return ret;
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}
|
|
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if (n > 0)
|
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rte_mov64((uint8_t *)dst - 64 + n,
|
|
|
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(const uint8_t *)src - 64 + n);
|
|
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return ret;
|
|
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}
|
|
|
|
|
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/**
|
|
|
|
* Make store aligned when copy size exceeds 512 bytes
|
|
|
|
*/
|
|
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|
dstofss = ((uintptr_t)dst & 0x3F);
|
|
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if (dstofss > 0) {
|
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dstofss = 64 - dstofss;
|
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n -= dstofss;
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rte_mov64((uint8_t *)dst, (const uint8_t *)src);
|
|
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src = (const uint8_t *)src + dstofss;
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dst = (uint8_t *)dst + dstofss;
|
|
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}
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/**
|
|
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|
* Copy 512-byte blocks.
|
|
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|
* Use copy block function for better instruction order control,
|
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* which is important when load is unaligned.
|
|
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*/
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rte_mov512blocks((uint8_t *)dst, (const uint8_t *)src, n);
|
|
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|
bits = n;
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n = n & 511;
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bits -= n;
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|
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src = (const uint8_t *)src + bits;
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dst = (uint8_t *)dst + bits;
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|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 128-byte blocks.
|
|
|
|
* Use copy block function for better instruction order control,
|
|
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|
* which is important when load is unaligned.
|
|
|
|
*/
|
|
|
|
if (n >= 128) {
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|
|
rte_mov128blocks((uint8_t *)dst, (const uint8_t *)src, n);
|
|
|
|
bits = n;
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|
n = n & 127;
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|
bits -= n;
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|
src = (const uint8_t *)src + bits;
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|
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|
dst = (uint8_t *)dst + bits;
|
|
|
|
}
|
|
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|
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|
|
|
/**
|
|
|
|
* Copy whatever left
|
|
|
|
*/
|
|
|
|
goto COPY_BLOCK_128_BACK63;
|
|
|
|
}
|
|
|
|
|
|
|
|
#elif defined RTE_MACHINE_CPUFLAG_AVX2
|
|
|
|
|
|
|
|
#define ALIGNMENT_MASK 0x1F
|
|
|
|
|
|
|
|
/**
|
|
|
|
* AVX2 implementation below
|
|
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|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 16 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov16(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
__m128i xmm0;
|
|
|
|
|
|
|
|
xmm0 = _mm_loadu_si128((const __m128i *)src);
|
|
|
|
_mm_storeu_si128((__m128i *)dst, xmm0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 32 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov32(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
__m256i ymm0;
|
|
|
|
|
|
|
|
ymm0 = _mm256_loadu_si256((const __m256i *)src);
|
|
|
|
_mm256_storeu_si256((__m256i *)dst, ymm0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 64 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov64(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
rte_mov32((uint8_t *)dst + 0 * 32, (const uint8_t *)src + 0 * 32);
|
|
|
|
rte_mov32((uint8_t *)dst + 1 * 32, (const uint8_t *)src + 1 * 32);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 128 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov128(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
rte_mov32((uint8_t *)dst + 0 * 32, (const uint8_t *)src + 0 * 32);
|
|
|
|
rte_mov32((uint8_t *)dst + 1 * 32, (const uint8_t *)src + 1 * 32);
|
|
|
|
rte_mov32((uint8_t *)dst + 2 * 32, (const uint8_t *)src + 2 * 32);
|
|
|
|
rte_mov32((uint8_t *)dst + 3 * 32, (const uint8_t *)src + 3 * 32);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 128-byte blocks from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov128blocks(uint8_t *dst, const uint8_t *src, size_t n)
|
|
|
|
{
|
|
|
|
__m256i ymm0, ymm1, ymm2, ymm3;
|
|
|
|
|
|
|
|
while (n >= 128) {
|
|
|
|
ymm0 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 0 * 32));
|
|
|
|
n -= 128;
|
|
|
|
ymm1 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 1 * 32));
|
|
|
|
ymm2 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 2 * 32));
|
|
|
|
ymm3 = _mm256_loadu_si256((const __m256i *)((const uint8_t *)src + 3 * 32));
|
|
|
|
src = (const uint8_t *)src + 128;
|
|
|
|
_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 0 * 32), ymm0);
|
|
|
|
_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 1 * 32), ymm1);
|
|
|
|
_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 2 * 32), ymm2);
|
|
|
|
_mm256_storeu_si256((__m256i *)((uint8_t *)dst + 3 * 32), ymm3);
|
|
|
|
dst = (uint8_t *)dst + 128;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline void *
|
|
|
|
rte_memcpy_generic(void *dst, const void *src, size_t n)
|
|
|
|
{
|
|
|
|
uintptr_t dstu = (uintptr_t)dst;
|
|
|
|
uintptr_t srcu = (uintptr_t)src;
|
|
|
|
void *ret = dst;
|
|
|
|
size_t dstofss;
|
|
|
|
size_t bits;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy less than 16 bytes
|
|
|
|
*/
|
|
|
|
if (n < 16) {
|
|
|
|
if (n & 0x01) {
|
|
|
|
*(uint8_t *)dstu = *(const uint8_t *)srcu;
|
|
|
|
srcu = (uintptr_t)((const uint8_t *)srcu + 1);
|
|
|
|
dstu = (uintptr_t)((uint8_t *)dstu + 1);
|
|
|
|
}
|
|
|
|
if (n & 0x02) {
|
|
|
|
*(uint16_t *)dstu = *(const uint16_t *)srcu;
|
|
|
|
srcu = (uintptr_t)((const uint16_t *)srcu + 1);
|
|
|
|
dstu = (uintptr_t)((uint16_t *)dstu + 1);
|
|
|
|
}
|
|
|
|
if (n & 0x04) {
|
|
|
|
*(uint32_t *)dstu = *(const uint32_t *)srcu;
|
|
|
|
srcu = (uintptr_t)((const uint32_t *)srcu + 1);
|
|
|
|
dstu = (uintptr_t)((uint32_t *)dstu + 1);
|
|
|
|
}
|
|
|
|
if (n & 0x08) {
|
|
|
|
*(uint64_t *)dstu = *(const uint64_t *)srcu;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Fast way when copy size doesn't exceed 256 bytes
|
|
|
|
*/
|
|
|
|
if (n <= 32) {
|
|
|
|
rte_mov16((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n,
|
|
|
|
(const uint8_t *)src - 16 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n <= 48) {
|
|
|
|
rte_mov16((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov16((uint8_t *)dst + 16, (const uint8_t *)src + 16);
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n,
|
|
|
|
(const uint8_t *)src - 16 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n <= 64) {
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov32((uint8_t *)dst - 32 + n,
|
|
|
|
(const uint8_t *)src - 32 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n <= 256) {
|
|
|
|
if (n >= 128) {
|
|
|
|
n -= 128;
|
|
|
|
rte_mov128((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
src = (const uint8_t *)src + 128;
|
|
|
|
dst = (uint8_t *)dst + 128;
|
|
|
|
}
|
|
|
|
COPY_BLOCK_128_BACK31:
|
|
|
|
if (n >= 64) {
|
|
|
|
n -= 64;
|
|
|
|
rte_mov64((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
src = (const uint8_t *)src + 64;
|
|
|
|
dst = (uint8_t *)dst + 64;
|
|
|
|
}
|
|
|
|
if (n > 32) {
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov32((uint8_t *)dst - 32 + n,
|
|
|
|
(const uint8_t *)src - 32 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n > 0) {
|
|
|
|
rte_mov32((uint8_t *)dst - 32 + n,
|
|
|
|
(const uint8_t *)src - 32 + n);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Make store aligned when copy size exceeds 256 bytes
|
|
|
|
*/
|
|
|
|
dstofss = (uintptr_t)dst & 0x1F;
|
|
|
|
if (dstofss > 0) {
|
|
|
|
dstofss = 32 - dstofss;
|
|
|
|
n -= dstofss;
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
src = (const uint8_t *)src + dstofss;
|
|
|
|
dst = (uint8_t *)dst + dstofss;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 128-byte blocks
|
|
|
|
*/
|
|
|
|
rte_mov128blocks((uint8_t *)dst, (const uint8_t *)src, n);
|
|
|
|
bits = n;
|
|
|
|
n = n & 127;
|
|
|
|
bits -= n;
|
|
|
|
src = (const uint8_t *)src + bits;
|
|
|
|
dst = (uint8_t *)dst + bits;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy whatever left
|
|
|
|
*/
|
|
|
|
goto COPY_BLOCK_128_BACK31;
|
|
|
|
}
|
|
|
|
|
|
|
|
#else /* RTE_MACHINE_CPUFLAG */
|
|
|
|
|
|
|
|
#define ALIGNMENT_MASK 0x0F
|
|
|
|
|
|
|
|
/**
|
|
|
|
* SSE & AVX implementation below
|
|
|
|
*/
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 16 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov16(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
__m128i xmm0;
|
|
|
|
|
|
|
|
xmm0 = _mm_loadu_si128((const __m128i *)(const __m128i *)src);
|
|
|
|
_mm_storeu_si128((__m128i *)dst, xmm0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 32 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov32(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 64 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov64(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 128 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov128(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 4 * 16, (const uint8_t *)src + 4 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 5 * 16, (const uint8_t *)src + 5 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 6 * 16, (const uint8_t *)src + 6 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 7 * 16, (const uint8_t *)src + 7 * 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy 256 bytes from one location to another,
|
|
|
|
* locations should not overlap.
|
|
|
|
*/
|
|
|
|
static inline void
|
|
|
|
rte_mov256(uint8_t *dst, const uint8_t *src)
|
|
|
|
{
|
|
|
|
rte_mov16((uint8_t *)dst + 0 * 16, (const uint8_t *)src + 0 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 1 * 16, (const uint8_t *)src + 1 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 2 * 16, (const uint8_t *)src + 2 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 3 * 16, (const uint8_t *)src + 3 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 4 * 16, (const uint8_t *)src + 4 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 5 * 16, (const uint8_t *)src + 5 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 6 * 16, (const uint8_t *)src + 6 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 7 * 16, (const uint8_t *)src + 7 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 8 * 16, (const uint8_t *)src + 8 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 9 * 16, (const uint8_t *)src + 9 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 10 * 16, (const uint8_t *)src + 10 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 11 * 16, (const uint8_t *)src + 11 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 12 * 16, (const uint8_t *)src + 12 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 13 * 16, (const uint8_t *)src + 13 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 14 * 16, (const uint8_t *)src + 14 * 16);
|
|
|
|
rte_mov16((uint8_t *)dst + 15 * 16, (const uint8_t *)src + 15 * 16);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Macro for copying unaligned block from one location to another with constant load offset,
|
|
|
|
* 47 bytes leftover maximum,
|
|
|
|
* locations should not overlap.
|
|
|
|
* Requirements:
|
|
|
|
* - Store is aligned
|
|
|
|
* - Load offset is <offset>, which must be immediate value within [1, 15]
|
|
|
|
* - For <src>, make sure <offset> bit backwards & <16 - offset> bit forwards are available for loading
|
|
|
|
* - <dst>, <src>, <len> must be variables
|
|
|
|
* - __m128i <xmm0> ~ <xmm8> must be pre-defined
|
|
|
|
*/
|
|
|
|
#define MOVEUNALIGNED_LEFT47_IMM(dst, src, len, offset) \
|
|
|
|
__extension__ ({ \
|
|
|
|
int tmp; \
|
|
|
|
while (len >= 128 + 16 - offset) { \
|
|
|
|
xmm0 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 0 * 16)); \
|
|
|
|
len -= 128; \
|
|
|
|
xmm1 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 1 * 16)); \
|
|
|
|
xmm2 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 2 * 16)); \
|
|
|
|
xmm3 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 3 * 16)); \
|
|
|
|
xmm4 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 4 * 16)); \
|
|
|
|
xmm5 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 5 * 16)); \
|
|
|
|
xmm6 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 6 * 16)); \
|
|
|
|
xmm7 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 7 * 16)); \
|
|
|
|
xmm8 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 8 * 16)); \
|
|
|
|
src = (const uint8_t *)src + 128; \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 0 * 16), _mm_alignr_epi8(xmm1, xmm0, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 1 * 16), _mm_alignr_epi8(xmm2, xmm1, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 2 * 16), _mm_alignr_epi8(xmm3, xmm2, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 3 * 16), _mm_alignr_epi8(xmm4, xmm3, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 4 * 16), _mm_alignr_epi8(xmm5, xmm4, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 5 * 16), _mm_alignr_epi8(xmm6, xmm5, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 6 * 16), _mm_alignr_epi8(xmm7, xmm6, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 7 * 16), _mm_alignr_epi8(xmm8, xmm7, offset)); \
|
|
|
|
dst = (uint8_t *)dst + 128; \
|
|
|
|
} \
|
|
|
|
tmp = len; \
|
|
|
|
len = ((len - 16 + offset) & 127) + 16 - offset; \
|
|
|
|
tmp -= len; \
|
|
|
|
src = (const uint8_t *)src + tmp; \
|
|
|
|
dst = (uint8_t *)dst + tmp; \
|
|
|
|
if (len >= 32 + 16 - offset) { \
|
|
|
|
while (len >= 32 + 16 - offset) { \
|
|
|
|
xmm0 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 0 * 16)); \
|
|
|
|
len -= 32; \
|
|
|
|
xmm1 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 1 * 16)); \
|
|
|
|
xmm2 = _mm_loadu_si128((const __m128i *)((const uint8_t *)src - offset + 2 * 16)); \
|
|
|
|
src = (const uint8_t *)src + 32; \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 0 * 16), _mm_alignr_epi8(xmm1, xmm0, offset)); \
|
|
|
|
_mm_storeu_si128((__m128i *)((uint8_t *)dst + 1 * 16), _mm_alignr_epi8(xmm2, xmm1, offset)); \
|
|
|
|
dst = (uint8_t *)dst + 32; \
|
|
|
|
} \
|
|
|
|
tmp = len; \
|
|
|
|
len = ((len - 16 + offset) & 31) + 16 - offset; \
|
|
|
|
tmp -= len; \
|
|
|
|
src = (const uint8_t *)src + tmp; \
|
|
|
|
dst = (uint8_t *)dst + tmp; \
|
|
|
|
} \
|
|
|
|
})
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Macro for copying unaligned block from one location to another,
|
|
|
|
* 47 bytes leftover maximum,
|
|
|
|
* locations should not overlap.
|
|
|
|
* Use switch here because the aligning instruction requires immediate value for shift count.
|
|
|
|
* Requirements:
|
|
|
|
* - Store is aligned
|
|
|
|
* - Load offset is <offset>, which must be within [1, 15]
|
|
|
|
* - For <src>, make sure <offset> bit backwards & <16 - offset> bit forwards are available for loading
|
|
|
|
* - <dst>, <src>, <len> must be variables
|
|
|
|
* - __m128i <xmm0> ~ <xmm8> used in MOVEUNALIGNED_LEFT47_IMM must be pre-defined
|
|
|
|
*/
|
|
|
|
#define MOVEUNALIGNED_LEFT47(dst, src, len, offset) \
|
|
|
|
__extension__ ({ \
|
|
|
|
switch (offset) { \
|
|
|
|
case 0x01: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x01); break; \
|
|
|
|
case 0x02: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x02); break; \
|
|
|
|
case 0x03: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x03); break; \
|
|
|
|
case 0x04: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x04); break; \
|
|
|
|
case 0x05: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x05); break; \
|
|
|
|
case 0x06: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x06); break; \
|
|
|
|
case 0x07: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x07); break; \
|
|
|
|
case 0x08: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x08); break; \
|
|
|
|
case 0x09: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x09); break; \
|
|
|
|
case 0x0A: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0A); break; \
|
|
|
|
case 0x0B: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0B); break; \
|
|
|
|
case 0x0C: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0C); break; \
|
|
|
|
case 0x0D: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0D); break; \
|
|
|
|
case 0x0E: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0E); break; \
|
|
|
|
case 0x0F: MOVEUNALIGNED_LEFT47_IMM(dst, src, n, 0x0F); break; \
|
|
|
|
default:; \
|
|
|
|
} \
|
|
|
|
})
|
|
|
|
|
|
|
|
static inline void *
|
|
|
|
rte_memcpy_generic(void *dst, const void *src, size_t n)
|
|
|
|
{
|
|
|
|
__m128i xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7, xmm8;
|
|
|
|
uintptr_t dstu = (uintptr_t)dst;
|
|
|
|
uintptr_t srcu = (uintptr_t)src;
|
|
|
|
void *ret = dst;
|
|
|
|
size_t dstofss;
|
|
|
|
size_t srcofs;
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy less than 16 bytes
|
|
|
|
*/
|
|
|
|
if (n < 16) {
|
|
|
|
if (n & 0x01) {
|
|
|
|
*(uint8_t *)dstu = *(const uint8_t *)srcu;
|
|
|
|
srcu = (uintptr_t)((const uint8_t *)srcu + 1);
|
|
|
|
dstu = (uintptr_t)((uint8_t *)dstu + 1);
|
|
|
|
}
|
|
|
|
if (n & 0x02) {
|
|
|
|
*(uint16_t *)dstu = *(const uint16_t *)srcu;
|
|
|
|
srcu = (uintptr_t)((const uint16_t *)srcu + 1);
|
|
|
|
dstu = (uintptr_t)((uint16_t *)dstu + 1);
|
|
|
|
}
|
|
|
|
if (n & 0x04) {
|
|
|
|
*(uint32_t *)dstu = *(const uint32_t *)srcu;
|
|
|
|
srcu = (uintptr_t)((const uint32_t *)srcu + 1);
|
|
|
|
dstu = (uintptr_t)((uint32_t *)dstu + 1);
|
|
|
|
}
|
|
|
|
if (n & 0x08) {
|
|
|
|
*(uint64_t *)dstu = *(const uint64_t *)srcu;
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Fast way when copy size doesn't exceed 512 bytes
|
|
|
|
*/
|
|
|
|
if (n <= 32) {
|
|
|
|
rte_mov16((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n <= 48) {
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n <= 64) {
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov16((uint8_t *)dst + 32, (const uint8_t *)src + 32);
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n <= 128) {
|
|
|
|
goto COPY_BLOCK_128_BACK15;
|
|
|
|
}
|
|
|
|
if (n <= 512) {
|
|
|
|
if (n >= 256) {
|
|
|
|
n -= 256;
|
|
|
|
rte_mov128((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov128((uint8_t *)dst + 128, (const uint8_t *)src + 128);
|
|
|
|
src = (const uint8_t *)src + 256;
|
|
|
|
dst = (uint8_t *)dst + 256;
|
|
|
|
}
|
|
|
|
COPY_BLOCK_255_BACK15:
|
|
|
|
if (n >= 128) {
|
|
|
|
n -= 128;
|
|
|
|
rte_mov128((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
src = (const uint8_t *)src + 128;
|
|
|
|
dst = (uint8_t *)dst + 128;
|
|
|
|
}
|
|
|
|
COPY_BLOCK_128_BACK15:
|
|
|
|
if (n >= 64) {
|
|
|
|
n -= 64;
|
|
|
|
rte_mov64((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
src = (const uint8_t *)src + 64;
|
|
|
|
dst = (uint8_t *)dst + 64;
|
|
|
|
}
|
|
|
|
COPY_BLOCK_64_BACK15:
|
|
|
|
if (n >= 32) {
|
|
|
|
n -= 32;
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
src = (const uint8_t *)src + 32;
|
|
|
|
dst = (uint8_t *)dst + 32;
|
|
|
|
}
|
|
|
|
if (n > 16) {
|
|
|
|
rte_mov16((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
if (n > 0) {
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n, (const uint8_t *)src - 16 + n);
|
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Make store aligned when copy size exceeds 512 bytes,
|
|
|
|
* and make sure the first 15 bytes are copied, because
|
|
|
|
* unaligned copy functions require up to 15 bytes
|
|
|
|
* backwards access.
|
|
|
|
*/
|
|
|
|
dstofss = (uintptr_t)dst & 0x0F;
|
|
|
|
if (dstofss > 0) {
|
|
|
|
dstofss = 16 - dstofss + 16;
|
|
|
|
n -= dstofss;
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
src = (const uint8_t *)src + dstofss;
|
|
|
|
dst = (uint8_t *)dst + dstofss;
|
|
|
|
}
|
|
|
|
srcofs = ((uintptr_t)src & 0x0F);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* For aligned copy
|
|
|
|
*/
|
|
|
|
if (srcofs == 0) {
|
|
|
|
/**
|
|
|
|
* Copy 256-byte blocks
|
|
|
|
*/
|
|
|
|
for (; n >= 256; n -= 256) {
|
|
|
|
rte_mov256((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
dst = (uint8_t *)dst + 256;
|
|
|
|
src = (const uint8_t *)src + 256;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy whatever left
|
|
|
|
*/
|
|
|
|
goto COPY_BLOCK_255_BACK15;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* For copy with unaligned load
|
|
|
|
*/
|
|
|
|
MOVEUNALIGNED_LEFT47(dst, src, n, srcofs);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Copy whatever left
|
|
|
|
*/
|
|
|
|
goto COPY_BLOCK_64_BACK15;
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif /* RTE_MACHINE_CPUFLAG */
|
|
|
|
|
|
|
|
static inline void *
|
|
|
|
rte_memcpy_aligned(void *dst, const void *src, size_t n)
|
|
|
|
{
|
|
|
|
void *ret = dst;
|
|
|
|
|
|
|
|
/* Copy size <= 16 bytes */
|
|
|
|
if (n < 16) {
|
|
|
|
if (n & 0x01) {
|
|
|
|
*(uint8_t *)dst = *(const uint8_t *)src;
|
|
|
|
src = (const uint8_t *)src + 1;
|
|
|
|
dst = (uint8_t *)dst + 1;
|
|
|
|
}
|
|
|
|
if (n & 0x02) {
|
|
|
|
*(uint16_t *)dst = *(const uint16_t *)src;
|
|
|
|
src = (const uint16_t *)src + 1;
|
|
|
|
dst = (uint16_t *)dst + 1;
|
|
|
|
}
|
|
|
|
if (n & 0x04) {
|
|
|
|
*(uint32_t *)dst = *(const uint32_t *)src;
|
|
|
|
src = (const uint32_t *)src + 1;
|
|
|
|
dst = (uint32_t *)dst + 1;
|
|
|
|
}
|
|
|
|
if (n & 0x08)
|
|
|
|
*(uint64_t *)dst = *(const uint64_t *)src;
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy 16 <= size <= 32 bytes */
|
|
|
|
if (n <= 32) {
|
|
|
|
rte_mov16((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov16((uint8_t *)dst - 16 + n,
|
|
|
|
(const uint8_t *)src - 16 + n);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy 32 < size <= 64 bytes */
|
|
|
|
if (n <= 64) {
|
|
|
|
rte_mov32((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
rte_mov32((uint8_t *)dst - 32 + n,
|
|
|
|
(const uint8_t *)src - 32 + n);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy 64 bytes blocks */
|
|
|
|
for (; n >= 64; n -= 64) {
|
|
|
|
rte_mov64((uint8_t *)dst, (const uint8_t *)src);
|
|
|
|
dst = (uint8_t *)dst + 64;
|
|
|
|
src = (const uint8_t *)src + 64;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Copy whatever left */
|
|
|
|
rte_mov64((uint8_t *)dst - 64 + n,
|
|
|
|
(const uint8_t *)src - 64 + n);
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
eal: optimize aligned memcpy on x86
This patch optimizes rte_memcpy for well aligned cases, where both
dst and src addr are aligned to maximum MOV width. It introduces a
dedicated function called rte_memcpy_aligned to handle the aligned
cases with simplified instruction stream. The existing rte_memcpy
is renamed as rte_memcpy_generic. The selection between them 2 is
done at the entry of rte_memcpy.
The existing rte_memcpy is for generic cases, it handles unaligned
copies and make store aligned, it even makes load aligned for micro
architectures like Ivy Bridge. However alignment handling comes at
a price: It adds extra load/store instructions, which can cause
complications sometime.
DPDK Vhost memcpy with Mergeable Rx Buffer feature as an example:
The copy is aligned, and remote, and there is header write along
which is also remote. In this case the memcpy instruction stream
should be simplified, to reduce extra load/store, therefore reduce
the probability of load/store buffer full caused pipeline stall, to
let the actual memcpy instructions be issued and let H/W prefetcher
goes to work as early as possible.
This patch is tested on Ivy Bridge, Haswell and Skylake, it provides
up to 20% gain for Virtio Vhost PVP traffic, with packet size ranging
from 64 to 1500 bytes.
The test can also be conducted without NIC, by setting loopback
traffic between Virtio and Vhost. For example, modify the macro
TXONLY_DEF_PACKET_LEN to the requested packet size in testpmd.h,
rebuild and start testpmd in both host and guest, then "start" on
one side and "start tx_first 32" on the other.
Signed-off-by: Zhihong Wang <zhihong.wang@intel.com>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Tested-by: Lei Yao <lei.a.yao@intel.com>
2016-12-06 20:31:06 -05:00
|
|
|
|
|
|
|
static inline void *
|
|
|
|
rte_memcpy(void *dst, const void *src, size_t n)
|
|
|
|
{
|
2017-11-03 20:47:23 +08:00
|
|
|
if (!(((uintptr_t)dst | (uintptr_t)src) & ALIGNMENT_MASK))
|
|
|
|
return rte_memcpy_aligned(dst, src, n);
|
eal: optimize aligned memcpy on x86
This patch optimizes rte_memcpy for well aligned cases, where both
dst and src addr are aligned to maximum MOV width. It introduces a
dedicated function called rte_memcpy_aligned to handle the aligned
cases with simplified instruction stream. The existing rte_memcpy
is renamed as rte_memcpy_generic. The selection between them 2 is
done at the entry of rte_memcpy.
The existing rte_memcpy is for generic cases, it handles unaligned
copies and make store aligned, it even makes load aligned for micro
architectures like Ivy Bridge. However alignment handling comes at
a price: It adds extra load/store instructions, which can cause
complications sometime.
DPDK Vhost memcpy with Mergeable Rx Buffer feature as an example:
The copy is aligned, and remote, and there is header write along
which is also remote. In this case the memcpy instruction stream
should be simplified, to reduce extra load/store, therefore reduce
the probability of load/store buffer full caused pipeline stall, to
let the actual memcpy instructions be issued and let H/W prefetcher
goes to work as early as possible.
This patch is tested on Ivy Bridge, Haswell and Skylake, it provides
up to 20% gain for Virtio Vhost PVP traffic, with packet size ranging
from 64 to 1500 bytes.
The test can also be conducted without NIC, by setting loopback
traffic between Virtio and Vhost. For example, modify the macro
TXONLY_DEF_PACKET_LEN to the requested packet size in testpmd.h,
rebuild and start testpmd in both host and guest, then "start" on
one side and "start tx_first 32" on the other.
Signed-off-by: Zhihong Wang <zhihong.wang@intel.com>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Tested-by: Lei Yao <lei.a.yao@intel.com>
2016-12-06 20:31:06 -05:00
|
|
|
else
|
2017-11-03 20:47:23 +08:00
|
|
|
return rte_memcpy_generic(dst, src, n);
|
eal: optimize aligned memcpy on x86
This patch optimizes rte_memcpy for well aligned cases, where both
dst and src addr are aligned to maximum MOV width. It introduces a
dedicated function called rte_memcpy_aligned to handle the aligned
cases with simplified instruction stream. The existing rte_memcpy
is renamed as rte_memcpy_generic. The selection between them 2 is
done at the entry of rte_memcpy.
The existing rte_memcpy is for generic cases, it handles unaligned
copies and make store aligned, it even makes load aligned for micro
architectures like Ivy Bridge. However alignment handling comes at
a price: It adds extra load/store instructions, which can cause
complications sometime.
DPDK Vhost memcpy with Mergeable Rx Buffer feature as an example:
The copy is aligned, and remote, and there is header write along
which is also remote. In this case the memcpy instruction stream
should be simplified, to reduce extra load/store, therefore reduce
the probability of load/store buffer full caused pipeline stall, to
let the actual memcpy instructions be issued and let H/W prefetcher
goes to work as early as possible.
This patch is tested on Ivy Bridge, Haswell and Skylake, it provides
up to 20% gain for Virtio Vhost PVP traffic, with packet size ranging
from 64 to 1500 bytes.
The test can also be conducted without NIC, by setting loopback
traffic between Virtio and Vhost. For example, modify the macro
TXONLY_DEF_PACKET_LEN to the requested packet size in testpmd.h,
rebuild and start testpmd in both host and guest, then "start" on
one side and "start tx_first 32" on the other.
Signed-off-by: Zhihong Wang <zhihong.wang@intel.com>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Tested-by: Lei Yao <lei.a.yao@intel.com>
2016-12-06 20:31:06 -05:00
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}
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2012-09-04 13:54:00 +01:00
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#ifdef __cplusplus
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}
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#endif
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2014-10-28 13:50:54 +01:00
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#endif /* _RTE_MEMCPY_X86_64_H_ */
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