2018-01-29 13:11:30 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2015 6WIND S.A.
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2018-03-20 19:20:35 +00:00
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* Copyright 2015 Mellanox Technologies, Ltd
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2015-10-30 18:52:30 +00:00
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*/
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2017-10-06 15:45:49 +00:00
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#define _GNU_SOURCE
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2015-10-30 18:52:30 +00:00
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#include <stddef.h>
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2015-10-30 18:52:33 +00:00
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#include <assert.h>
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2018-02-08 16:37:06 +00:00
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#include <inttypes.h>
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2015-10-30 18:52:30 +00:00
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#include <unistd.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <errno.h>
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#include <dirent.h>
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#include <net/if.h>
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#include <sys/ioctl.h>
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#include <sys/socket.h>
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#include <netinet/in.h>
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2015-10-30 18:52:38 +00:00
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#include <linux/ethtool.h>
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#include <linux/sockios.h>
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2015-10-30 18:57:23 +00:00
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#include <fcntl.h>
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2017-08-30 14:47:06 +00:00
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#include <stdalign.h>
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2017-10-06 15:45:49 +00:00
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#include <sys/un.h>
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2018-03-12 13:43:19 +00:00
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#include <time.h>
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2015-10-30 18:52:30 +00:00
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#include <rte_atomic.h>
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2018-01-22 00:16:22 +00:00
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#include <rte_ethdev_driver.h>
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2017-10-26 10:06:08 +00:00
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#include <rte_bus_pci.h>
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2015-10-30 18:52:30 +00:00
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#include <rte_mbuf.h>
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#include <rte_common.h>
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2015-10-30 18:57:23 +00:00
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#include <rte_interrupts.h>
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2016-03-17 15:38:55 +00:00
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#include <rte_malloc.h>
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2018-03-12 11:33:00 +00:00
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#include <rte_string_fns.h>
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net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
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#include <rte_rwlock.h>
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2015-10-30 18:52:30 +00:00
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#include "mlx5.h"
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2018-01-30 15:34:56 +00:00
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#include "mlx5_glue.h"
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2015-10-30 18:52:33 +00:00
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#include "mlx5_rxtx.h"
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2015-10-30 18:52:30 +00:00
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#include "mlx5_utils.h"
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2017-02-09 12:29:54 +00:00
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/* Add defines in case the running kernel is not the same as user headers. */
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#ifndef ETHTOOL_GLINKSETTINGS
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struct ethtool_link_settings {
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uint32_t cmd;
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uint32_t speed;
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uint8_t duplex;
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uint8_t port;
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uint8_t phy_address;
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uint8_t autoneg;
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uint8_t mdio_support;
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uint8_t eth_to_mdix;
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uint8_t eth_tp_mdix_ctrl;
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int8_t link_mode_masks_nwords;
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uint32_t reserved[8];
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uint32_t link_mode_masks[];
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};
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#define ETHTOOL_GLINKSETTINGS 0x0000004c
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#define ETHTOOL_LINK_MODE_1000baseT_Full_BIT 5
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#define ETHTOOL_LINK_MODE_Autoneg_BIT 6
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#define ETHTOOL_LINK_MODE_1000baseKX_Full_BIT 17
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#define ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT 18
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#define ETHTOOL_LINK_MODE_10000baseKR_Full_BIT 19
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#define ETHTOOL_LINK_MODE_10000baseR_FEC_BIT 20
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#define ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT 21
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#define ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT 22
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#define ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT 23
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#define ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT 24
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#define ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT 25
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#define ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT 26
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#define ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT 27
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#define ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT 28
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#define ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT 29
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#define ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT 30
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#endif
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#ifndef HAVE_ETHTOOL_LINK_MODE_25G
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#define ETHTOOL_LINK_MODE_25000baseCR_Full_BIT 31
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#define ETHTOOL_LINK_MODE_25000baseKR_Full_BIT 32
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#define ETHTOOL_LINK_MODE_25000baseSR_Full_BIT 33
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#endif
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#ifndef HAVE_ETHTOOL_LINK_MODE_50G
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#define ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT 34
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#define ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT 35
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#endif
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#ifndef HAVE_ETHTOOL_LINK_MODE_100G
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#define ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT 36
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#define ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT 37
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#define ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT 38
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#define ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT 39
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#endif
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2015-10-30 18:52:30 +00:00
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/**
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* Get interface name from private structure.
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*
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2018-03-05 12:21:04 +00:00
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* @param[in] dev
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* Pointer to Ethernet device.
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2015-10-30 18:52:30 +00:00
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* @param[out] ifname
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* Interface name output buffer.
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*
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* @return
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2018-03-05 12:21:06 +00:00
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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2015-10-30 18:52:30 +00:00
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*/
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int
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2018-03-05 12:21:04 +00:00
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mlx5_get_ifname(const struct rte_eth_dev *dev, char (*ifname)[IF_NAMESIZE])
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2015-10-30 18:52:30 +00:00
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{
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2018-03-05 12:21:04 +00:00
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struct priv *priv = dev->data->dev_private;
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2015-10-30 18:52:30 +00:00
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DIR *dir;
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struct dirent *dent;
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unsigned int dev_type = 0;
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unsigned int dev_port_prev = ~0u;
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char match[IF_NAMESIZE] = "";
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{
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2017-10-06 15:45:51 +00:00
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MKSTR(path, "%s/device/net", priv->ibdev_path);
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2015-10-30 18:52:30 +00:00
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dir = opendir(path);
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2018-03-05 12:21:06 +00:00
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if (dir == NULL) {
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rte_errno = errno;
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return -rte_errno;
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}
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2015-10-30 18:52:30 +00:00
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}
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while ((dent = readdir(dir)) != NULL) {
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char *name = dent->d_name;
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FILE *file;
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unsigned int dev_port;
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int r;
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if ((name[0] == '.') &&
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((name[1] == '\0') ||
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((name[1] == '.') && (name[2] == '\0'))))
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continue;
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MKSTR(path, "%s/device/net/%s/%s",
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2017-10-06 15:45:51 +00:00
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priv->ibdev_path, name,
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2015-10-30 18:52:30 +00:00
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(dev_type ? "dev_id" : "dev_port"));
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file = fopen(path, "rb");
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if (file == NULL) {
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if (errno != ENOENT)
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continue;
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/*
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* Switch to dev_id when dev_port does not exist as
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* is the case with Linux kernel versions < 3.15.
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*/
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try_dev_id:
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match[0] = '\0';
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if (dev_type)
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break;
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dev_type = 1;
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dev_port_prev = ~0u;
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rewinddir(dir);
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continue;
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}
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r = fscanf(file, (dev_type ? "%x" : "%u"), &dev_port);
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fclose(file);
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if (r != 1)
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continue;
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/*
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* Switch to dev_id when dev_port returns the same value for
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* all ports. May happen when using a MOFED release older than
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* 3.0 with a Linux kernel >= 3.15.
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*/
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if (dev_port == dev_port_prev)
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goto try_dev_id;
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dev_port_prev = dev_port;
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if (dev_port == (priv->port - 1u))
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2018-03-12 11:33:00 +00:00
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strlcpy(match, name, sizeof(match));
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2015-10-30 18:52:30 +00:00
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}
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closedir(dir);
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2018-03-05 12:21:06 +00:00
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if (match[0] == '\0') {
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rte_errno = ENOENT;
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return -rte_errno;
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}
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2015-10-30 18:52:30 +00:00
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strncpy(*ifname, match, sizeof(*ifname));
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return 0;
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}
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2018-04-05 15:07:19 +00:00
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/**
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* Get the interface index from device name.
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*
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* @param[in] dev
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* Pointer to Ethernet device.
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*
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* @return
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* Interface index on success, a negative errno value otherwise and
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* rte_errno is set.
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*/
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int
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mlx5_ifindex(const struct rte_eth_dev *dev)
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{
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char ifname[IF_NAMESIZE];
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2018-06-27 09:20:52 +00:00
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unsigned int ret;
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2018-04-05 15:07:19 +00:00
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ret = mlx5_get_ifname(dev, &ifname);
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if (ret)
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return ret;
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ret = if_nametoindex(ifname);
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2018-06-27 09:20:52 +00:00
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if (ret == 0) {
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2018-04-05 15:07:19 +00:00
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rte_errno = errno;
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return -rte_errno;
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}
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return ret;
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}
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2015-10-30 18:52:30 +00:00
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/**
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* Perform ifreq ioctl() on associated Ethernet device.
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*
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2018-03-05 12:21:04 +00:00
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* @param[in] dev
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* Pointer to Ethernet device.
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2015-10-30 18:52:30 +00:00
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* @param req
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* Request number to pass to ioctl().
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* @param[out] ifr
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* Interface request structure output buffer.
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*
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* @return
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2018-03-05 12:21:06 +00:00
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* 0 on success, a negative errno value otherwise and rte_errno is set.
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2015-10-30 18:52:30 +00:00
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*/
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int
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2018-03-05 12:21:04 +00:00
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mlx5_ifreq(const struct rte_eth_dev *dev, int req, struct ifreq *ifr)
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2015-10-30 18:52:30 +00:00
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{
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int sock = socket(PF_INET, SOCK_DGRAM, IPPROTO_IP);
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2018-03-05 12:21:06 +00:00
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int ret = 0;
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2015-10-30 18:52:30 +00:00
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2018-03-05 12:21:06 +00:00
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if (sock == -1) {
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rte_errno = errno;
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return -rte_errno;
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}
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ret = mlx5_get_ifname(dev, &ifr->ifr_name);
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if (ret)
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goto error;
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ret = ioctl(sock, req, ifr);
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if (ret == -1) {
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rte_errno = errno;
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goto error;
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}
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2015-10-30 18:52:30 +00:00
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close(sock);
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2018-03-05 12:21:06 +00:00
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return 0;
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error:
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close(sock);
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return -rte_errno;
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2015-10-30 18:52:30 +00:00
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}
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/**
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* Get device MTU.
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*
|
2018-03-05 12:21:04 +00:00
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* @param dev
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* Pointer to Ethernet device.
|
2015-10-30 18:52:30 +00:00
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* @param[out] mtu
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* MTU value output buffer.
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*
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* @return
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2018-03-05 12:21:06 +00:00
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* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:30 +00:00
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*/
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int
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2018-03-05 12:21:04 +00:00
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mlx5_get_mtu(struct rte_eth_dev *dev, uint16_t *mtu)
|
2015-10-30 18:52:30 +00:00
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{
|
2018-02-08 16:37:06 +00:00
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struct ifreq request;
|
2018-03-05 12:21:04 +00:00
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int ret = mlx5_ifreq(dev, SIOCGIFMTU, &request);
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2015-10-30 18:52:30 +00:00
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2018-02-08 16:37:06 +00:00
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if (ret)
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return ret;
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*mtu = request.ifr_mtu;
|
2017-02-14 14:31:06 +00:00
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return 0;
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}
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|
2015-10-30 18:52:35 +00:00
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/**
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* Set device MTU.
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*
|
2018-03-05 12:21:04 +00:00
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* @param dev
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* Pointer to Ethernet device.
|
2015-10-30 18:52:35 +00:00
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* @param mtu
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* MTU value to set.
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*
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* @return
|
2018-03-05 12:21:06 +00:00
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* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:35 +00:00
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*/
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static int
|
2018-03-05 12:21:04 +00:00
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mlx5_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
|
2015-10-30 18:52:35 +00:00
|
|
|
{
|
2018-02-08 16:37:06 +00:00
|
|
|
struct ifreq request = { .ifr_mtu = mtu, };
|
2016-06-08 09:43:26 +00:00
|
|
|
|
2018-03-05 12:21:04 +00:00
|
|
|
return mlx5_ifreq(dev, SIOCSIFMTU, &request);
|
2015-10-30 18:52:35 +00:00
|
|
|
}
|
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
/**
|
|
|
|
* Set device flags.
|
|
|
|
*
|
2018-03-05 12:21:04 +00:00
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device.
|
2015-10-30 18:52:30 +00:00
|
|
|
* @param keep
|
|
|
|
* Bitmask for flags that must remain untouched.
|
|
|
|
* @param flags
|
|
|
|
* Bitmask for flags to modify.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:30 +00:00
|
|
|
*/
|
|
|
|
int
|
2018-03-05 12:21:04 +00:00
|
|
|
mlx5_set_flags(struct rte_eth_dev *dev, unsigned int keep, unsigned int flags)
|
2015-10-30 18:52:30 +00:00
|
|
|
{
|
2018-02-08 16:37:06 +00:00
|
|
|
struct ifreq request;
|
2018-03-05 12:21:04 +00:00
|
|
|
int ret = mlx5_ifreq(dev, SIOCGIFFLAGS, &request);
|
2015-10-30 18:52:30 +00:00
|
|
|
|
2018-02-08 16:37:06 +00:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
request.ifr_flags &= keep;
|
|
|
|
request.ifr_flags |= flags & ~keep;
|
2018-03-05 12:21:04 +00:00
|
|
|
return mlx5_ifreq(dev, SIOCSIFFLAGS, &request);
|
2015-10-30 18:52:30 +00:00
|
|
|
}
|
|
|
|
|
2015-10-30 18:52:33 +00:00
|
|
|
/**
|
2018-03-05 12:21:03 +00:00
|
|
|
* DPDK callback for Ethernet device configuration.
|
2015-10-30 18:52:33 +00:00
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:33 +00:00
|
|
|
*/
|
2018-03-05 12:21:03 +00:00
|
|
|
int
|
|
|
|
mlx5_dev_configure(struct rte_eth_dev *dev)
|
2015-10-30 18:52:33 +00:00
|
|
|
{
|
|
|
|
struct priv *priv = dev->data->dev_private;
|
|
|
|
unsigned int rxqs_n = dev->data->nb_rx_queues;
|
|
|
|
unsigned int txqs_n = dev->data->nb_tx_queues;
|
2015-11-02 18:11:57 +00:00
|
|
|
unsigned int i;
|
|
|
|
unsigned int j;
|
|
|
|
unsigned int reta_idx_n;
|
2017-10-09 14:44:56 +00:00
|
|
|
const uint8_t use_app_rss_key =
|
2017-12-26 07:40:41 +00:00
|
|
|
!!dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key;
|
2018-03-05 12:21:06 +00:00
|
|
|
int ret = 0;
|
2018-01-10 09:17:00 +00:00
|
|
|
|
2017-10-09 14:44:56 +00:00
|
|
|
if (use_app_rss_key &&
|
|
|
|
(dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key_len !=
|
|
|
|
rss_hash_default_key_len)) {
|
2018-03-26 10:12:18 +00:00
|
|
|
DRV_LOG(ERR, "port %u RSS key len must be %zu Bytes long",
|
|
|
|
dev->data->port_id, rss_hash_default_key_len);
|
2018-03-05 12:21:06 +00:00
|
|
|
rte_errno = EINVAL;
|
|
|
|
return -rte_errno;
|
2017-10-09 14:44:56 +00:00
|
|
|
}
|
|
|
|
priv->rss_conf.rss_key =
|
|
|
|
rte_realloc(priv->rss_conf.rss_key,
|
|
|
|
rss_hash_default_key_len, 0);
|
|
|
|
if (!priv->rss_conf.rss_key) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(ERR, "port %u cannot allocate RSS hash key memory (%u)",
|
|
|
|
dev->data->port_id, rxqs_n);
|
2018-03-05 12:21:06 +00:00
|
|
|
rte_errno = ENOMEM;
|
|
|
|
return -rte_errno;
|
2017-10-09 14:44:56 +00:00
|
|
|
}
|
|
|
|
memcpy(priv->rss_conf.rss_key,
|
|
|
|
use_app_rss_key ?
|
|
|
|
dev->data->dev_conf.rx_adv_conf.rss_conf.rss_key :
|
|
|
|
rss_hash_default_key,
|
|
|
|
rss_hash_default_key_len);
|
|
|
|
priv->rss_conf.rss_key_len = rss_hash_default_key_len;
|
|
|
|
priv->rss_conf.rss_hf = dev->data->dev_conf.rx_adv_conf.rss_conf.rss_hf;
|
2015-10-30 18:52:33 +00:00
|
|
|
priv->rxqs = (void *)dev->data->rx_queues;
|
|
|
|
priv->txqs = (void *)dev->data->tx_queues;
|
|
|
|
if (txqs_n != priv->txqs_n) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(INFO, "port %u Tx queues number update: %u -> %u",
|
|
|
|
dev->data->port_id, priv->txqs_n, txqs_n);
|
2015-10-30 18:52:33 +00:00
|
|
|
priv->txqs_n = txqs_n;
|
|
|
|
}
|
2018-01-10 09:16:58 +00:00
|
|
|
if (rxqs_n > priv->config.ind_table_max_size) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(ERR, "port %u cannot handle this many Rx queues (%u)",
|
|
|
|
dev->data->port_id, rxqs_n);
|
2018-03-05 12:21:06 +00:00
|
|
|
rte_errno = EINVAL;
|
|
|
|
return -rte_errno;
|
2015-11-02 18:11:57 +00:00
|
|
|
}
|
2015-10-30 18:52:33 +00:00
|
|
|
if (rxqs_n == priv->rxqs_n)
|
|
|
|
return 0;
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(INFO, "port %u Rx queues number update: %u -> %u",
|
|
|
|
dev->data->port_id, priv->rxqs_n, rxqs_n);
|
2015-10-30 18:52:33 +00:00
|
|
|
priv->rxqs_n = rxqs_n;
|
2015-11-02 18:11:57 +00:00
|
|
|
/* If the requested number of RX queues is not a power of two, use the
|
|
|
|
* maximum indirection table size for better balancing.
|
|
|
|
* The result is always rounded to the next power of two. */
|
|
|
|
reta_idx_n = (1 << log2above((rxqs_n & (rxqs_n - 1)) ?
|
2018-01-10 09:16:58 +00:00
|
|
|
priv->config.ind_table_max_size :
|
2015-11-02 18:11:57 +00:00
|
|
|
rxqs_n));
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_rss_reta_index_resize(dev, reta_idx_n);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
2015-11-02 18:11:57 +00:00
|
|
|
/* When the number of RX queues is not a power of two, the remaining
|
|
|
|
* table entries are padded with reused WQs and hashes are not spread
|
|
|
|
* uniformly. */
|
|
|
|
for (i = 0, j = 0; (i != reta_idx_n); ++i) {
|
|
|
|
(*priv->reta_idx)[i] = j;
|
|
|
|
if (++j == rxqs_n)
|
|
|
|
j = 0;
|
|
|
|
}
|
2015-10-30 18:55:06 +00:00
|
|
|
return 0;
|
2015-10-30 18:52:33 +00:00
|
|
|
}
|
|
|
|
|
2018-05-01 09:58:49 +00:00
|
|
|
/**
|
|
|
|
* Sets default tuning parameters.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device.
|
|
|
|
* @param[out] info
|
|
|
|
* Info structure output buffer.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
mlx5_set_default_params(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
|
|
|
|
{
|
|
|
|
struct priv *priv = dev->data->dev_private;
|
|
|
|
|
|
|
|
/* Minimum CPU utilization. */
|
|
|
|
info->default_rxportconf.ring_size = 256;
|
|
|
|
info->default_txportconf.ring_size = 256;
|
|
|
|
info->default_rxportconf.burst_size = 64;
|
|
|
|
info->default_txportconf.burst_size = 64;
|
|
|
|
if (priv->link_speed_capa & ETH_LINK_SPEED_100G) {
|
|
|
|
info->default_rxportconf.nb_queues = 16;
|
|
|
|
info->default_txportconf.nb_queues = 16;
|
|
|
|
if (dev->data->nb_rx_queues > 2 ||
|
|
|
|
dev->data->nb_tx_queues > 2) {
|
|
|
|
/* Max Throughput. */
|
|
|
|
info->default_rxportconf.ring_size = 2048;
|
|
|
|
info->default_txportconf.ring_size = 2048;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
info->default_rxportconf.nb_queues = 8;
|
|
|
|
info->default_txportconf.nb_queues = 8;
|
|
|
|
if (dev->data->nb_rx_queues > 2 ||
|
|
|
|
dev->data->nb_tx_queues > 2) {
|
|
|
|
/* Max Throughput. */
|
|
|
|
info->default_rxportconf.ring_size = 4096;
|
|
|
|
info->default_txportconf.ring_size = 4096;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-10-30 18:52:33 +00:00
|
|
|
/**
|
|
|
|
* DPDK callback to get information about the device.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
* @param[out] info
|
|
|
|
* Info structure output buffer.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
mlx5_dev_infos_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *info)
|
|
|
|
{
|
2017-11-23 09:22:32 +00:00
|
|
|
struct priv *priv = dev->data->dev_private;
|
2018-01-10 09:16:58 +00:00
|
|
|
struct mlx5_dev_config *config = &priv->config;
|
2015-10-30 18:52:33 +00:00
|
|
|
unsigned int max;
|
|
|
|
char ifname[IF_NAMESIZE];
|
|
|
|
|
|
|
|
/* FIXME: we should ask the device for these values. */
|
|
|
|
info->min_rx_bufsize = 32;
|
|
|
|
info->max_rx_pktlen = 65536;
|
|
|
|
/*
|
|
|
|
* Since we need one CQ per QP, the limit is the minimum number
|
|
|
|
* between the two values.
|
|
|
|
*/
|
2017-09-26 15:38:24 +00:00
|
|
|
max = RTE_MIN(priv->device_attr.orig_attr.max_cq,
|
|
|
|
priv->device_attr.orig_attr.max_qp);
|
2015-10-30 18:52:33 +00:00
|
|
|
/* If max >= 65535 then max = 0, max_rx_queues is uint16_t. */
|
|
|
|
if (max >= 65535)
|
|
|
|
max = 65535;
|
|
|
|
info->max_rx_queues = max;
|
|
|
|
info->max_tx_queues = max;
|
2018-04-23 11:09:27 +00:00
|
|
|
info->max_mac_addrs = MLX5_MAX_UC_MAC_ADDRESSES;
|
2018-03-05 12:21:04 +00:00
|
|
|
info->rx_queue_offload_capa = mlx5_get_rx_queue_offloads(dev);
|
|
|
|
info->rx_offload_capa = (mlx5_get_rx_port_offloads() |
|
2018-01-10 09:17:01 +00:00
|
|
|
info->rx_queue_offload_capa);
|
2018-03-05 12:21:04 +00:00
|
|
|
info->tx_offload_capa = mlx5_get_tx_port_offloads(dev);
|
|
|
|
if (mlx5_get_ifname(dev, &ifname) == 0)
|
2015-10-30 18:52:33 +00:00
|
|
|
info->if_index = if_nametoindex(ifname);
|
2017-03-20 23:04:34 +00:00
|
|
|
info->reta_size = priv->reta_idx_n ?
|
2018-01-10 09:16:58 +00:00
|
|
|
priv->reta_idx_n : config->ind_table_max_size;
|
2018-03-26 10:12:19 +00:00
|
|
|
info->hash_key_size = rss_hash_default_key_len;
|
2016-10-26 09:44:01 +00:00
|
|
|
info->speed_capa = priv->link_speed_capa;
|
2018-01-22 20:52:14 +00:00
|
|
|
info->flow_type_rss_offloads = ~MLX5_RSS_HF_MASK;
|
2018-05-01 09:58:49 +00:00
|
|
|
mlx5_set_default_params(dev, info);
|
2015-10-30 18:52:33 +00:00
|
|
|
}
|
|
|
|
|
2018-03-05 12:21:01 +00:00
|
|
|
/**
|
|
|
|
* Get supported packet types.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* A pointer to the supported Packet types array.
|
|
|
|
*/
|
2016-03-14 20:50:50 +00:00
|
|
|
const uint32_t *
|
|
|
|
mlx5_dev_supported_ptypes_get(struct rte_eth_dev *dev)
|
|
|
|
{
|
|
|
|
static const uint32_t ptypes[] = {
|
|
|
|
/* refers to rxq_cq_to_pkt_type() */
|
2017-07-26 19:29:33 +00:00
|
|
|
RTE_PTYPE_L2_ETHER,
|
2017-02-24 09:16:56 +00:00
|
|
|
RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
|
|
|
|
RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
|
2017-07-26 19:29:33 +00:00
|
|
|
RTE_PTYPE_L4_NONFRAG,
|
|
|
|
RTE_PTYPE_L4_FRAG,
|
|
|
|
RTE_PTYPE_L4_TCP,
|
|
|
|
RTE_PTYPE_L4_UDP,
|
2017-02-24 09:16:56 +00:00
|
|
|
RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
|
|
|
|
RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
|
2017-07-26 19:29:33 +00:00
|
|
|
RTE_PTYPE_INNER_L4_NONFRAG,
|
|
|
|
RTE_PTYPE_INNER_L4_FRAG,
|
|
|
|
RTE_PTYPE_INNER_L4_TCP,
|
|
|
|
RTE_PTYPE_INNER_L4_UDP,
|
2016-03-14 20:50:50 +00:00
|
|
|
RTE_PTYPE_UNKNOWN
|
|
|
|
};
|
|
|
|
|
2017-07-06 18:41:10 +00:00
|
|
|
if (dev->rx_pkt_burst == mlx5_rx_burst ||
|
2018-05-09 11:13:50 +00:00
|
|
|
dev->rx_pkt_burst == mlx5_rx_burst_mprq ||
|
2017-07-06 18:41:10 +00:00
|
|
|
dev->rx_pkt_burst == mlx5_rx_burst_vec)
|
2016-03-14 20:50:50 +00:00
|
|
|
return ptypes;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2015-10-30 18:52:38 +00:00
|
|
|
/**
|
2017-01-11 16:44:01 +00:00
|
|
|
* DPDK callback to retrieve physical link information.
|
2015-10-30 18:52:38 +00:00
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
2018-03-12 13:43:19 +00:00
|
|
|
* @param[out] link
|
|
|
|
* Storage for current link status.
|
2018-03-05 12:21:01 +00:00
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:38 +00:00
|
|
|
*/
|
2016-10-26 09:44:02 +00:00
|
|
|
static int
|
2018-03-12 13:43:19 +00:00
|
|
|
mlx5_link_update_unlocked_gset(struct rte_eth_dev *dev,
|
|
|
|
struct rte_eth_link *link)
|
2015-10-30 18:52:38 +00:00
|
|
|
{
|
2017-11-23 09:22:32 +00:00
|
|
|
struct priv *priv = dev->data->dev_private;
|
2015-10-30 18:52:38 +00:00
|
|
|
struct ethtool_cmd edata = {
|
2016-10-26 09:44:01 +00:00
|
|
|
.cmd = ETHTOOL_GSET /* Deprecated since Linux v4.5. */
|
2015-10-30 18:52:38 +00:00
|
|
|
};
|
|
|
|
struct ifreq ifr;
|
|
|
|
struct rte_eth_link dev_link;
|
|
|
|
int link_speed = 0;
|
2018-03-05 12:21:06 +00:00
|
|
|
int ret;
|
2015-10-30 18:52:38 +00:00
|
|
|
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_ifreq(dev, SIOCGIFFLAGS, &ifr);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(WARNING, "port %u ioctl(SIOCGIFFLAGS) failed: %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2015-10-30 18:52:38 +00:00
|
|
|
}
|
|
|
|
memset(&dev_link, 0, sizeof(dev_link));
|
|
|
|
dev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&
|
|
|
|
(ifr.ifr_flags & IFF_RUNNING));
|
2016-06-20 13:31:46 +00:00
|
|
|
ifr.ifr_data = (void *)&edata;
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(WARNING,
|
|
|
|
"port %u ioctl(SIOCETHTOOL, ETHTOOL_GSET) failed: %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2015-10-30 18:52:38 +00:00
|
|
|
}
|
|
|
|
link_speed = ethtool_cmd_speed(&edata);
|
|
|
|
if (link_speed == -1)
|
2018-04-17 11:30:35 +00:00
|
|
|
dev_link.link_speed = ETH_SPEED_NUM_NONE;
|
2015-10-30 18:52:38 +00:00
|
|
|
else
|
|
|
|
dev_link.link_speed = link_speed;
|
2016-10-26 09:44:01 +00:00
|
|
|
priv->link_speed_capa = 0;
|
|
|
|
if (edata.supported & SUPPORTED_Autoneg)
|
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_AUTONEG;
|
|
|
|
if (edata.supported & (SUPPORTED_1000baseT_Full |
|
|
|
|
SUPPORTED_1000baseKX_Full))
|
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_1G;
|
|
|
|
if (edata.supported & SUPPORTED_10000baseKR_Full)
|
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_10G;
|
|
|
|
if (edata.supported & (SUPPORTED_40000baseKR4_Full |
|
|
|
|
SUPPORTED_40000baseCR4_Full |
|
|
|
|
SUPPORTED_40000baseSR4_Full |
|
|
|
|
SUPPORTED_40000baseLR4_Full))
|
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_40G;
|
2015-10-30 18:52:38 +00:00
|
|
|
dev_link.link_duplex = ((edata.duplex == DUPLEX_HALF) ?
|
|
|
|
ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);
|
2016-03-31 22:12:29 +00:00
|
|
|
dev_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
|
|
|
|
ETH_LINK_SPEED_FIXED);
|
2018-03-12 13:43:19 +00:00
|
|
|
if ((dev_link.link_speed && !dev_link.link_status) ||
|
|
|
|
(!dev_link.link_speed && dev_link.link_status)) {
|
|
|
|
rte_errno = EAGAIN;
|
|
|
|
return -rte_errno;
|
2015-10-30 18:52:38 +00:00
|
|
|
}
|
2018-03-12 13:43:19 +00:00
|
|
|
*link = dev_link;
|
|
|
|
return 0;
|
2015-10-30 18:52:38 +00:00
|
|
|
}
|
|
|
|
|
2016-10-26 09:44:02 +00:00
|
|
|
/**
|
2017-02-09 12:29:54 +00:00
|
|
|
* Retrieve physical link information (unlocked version using new ioctl).
|
2016-10-26 09:44:02 +00:00
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
2018-03-12 13:43:19 +00:00
|
|
|
* @param[out] link
|
|
|
|
* Storage for current link status.
|
2018-03-05 12:21:01 +00:00
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2016-10-26 09:44:02 +00:00
|
|
|
*/
|
|
|
|
static int
|
2018-03-12 13:43:19 +00:00
|
|
|
mlx5_link_update_unlocked_gs(struct rte_eth_dev *dev,
|
|
|
|
struct rte_eth_link *link)
|
|
|
|
|
2016-10-26 09:44:02 +00:00
|
|
|
{
|
2017-11-23 09:22:32 +00:00
|
|
|
struct priv *priv = dev->data->dev_private;
|
2017-08-30 14:47:07 +00:00
|
|
|
struct ethtool_link_settings gcmd = { .cmd = ETHTOOL_GLINKSETTINGS };
|
2016-10-26 09:44:02 +00:00
|
|
|
struct ifreq ifr;
|
|
|
|
struct rte_eth_link dev_link;
|
|
|
|
uint64_t sc;
|
2018-03-05 12:21:06 +00:00
|
|
|
int ret;
|
2016-10-26 09:44:02 +00:00
|
|
|
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_ifreq(dev, SIOCGIFFLAGS, &ifr);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(WARNING, "port %u ioctl(SIOCGIFFLAGS) failed: %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2016-10-26 09:44:02 +00:00
|
|
|
}
|
|
|
|
memset(&dev_link, 0, sizeof(dev_link));
|
|
|
|
dev_link.link_status = ((ifr.ifr_flags & IFF_UP) &&
|
|
|
|
(ifr.ifr_flags & IFF_RUNNING));
|
2017-08-30 14:47:07 +00:00
|
|
|
ifr.ifr_data = (void *)&gcmd;
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(DEBUG,
|
|
|
|
"port %u ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS)"
|
|
|
|
" failed: %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2016-10-26 09:44:02 +00:00
|
|
|
}
|
2017-08-30 14:47:07 +00:00
|
|
|
gcmd.link_mode_masks_nwords = -gcmd.link_mode_masks_nwords;
|
|
|
|
|
|
|
|
alignas(struct ethtool_link_settings)
|
|
|
|
uint8_t data[offsetof(struct ethtool_link_settings, link_mode_masks) +
|
|
|
|
sizeof(uint32_t) * gcmd.link_mode_masks_nwords * 3];
|
|
|
|
struct ethtool_link_settings *ecmd = (void *)data;
|
|
|
|
|
|
|
|
*ecmd = gcmd;
|
|
|
|
ifr.ifr_data = (void *)ecmd;
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(DEBUG,
|
|
|
|
"port %u ioctl(SIOCETHTOOL, ETHTOOL_GLINKSETTINGS)"
|
|
|
|
" failed: %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2017-07-25 13:38:07 +00:00
|
|
|
}
|
2017-08-30 14:47:06 +00:00
|
|
|
dev_link.link_speed = ecmd->speed;
|
|
|
|
sc = ecmd->link_mode_masks[0] |
|
|
|
|
((uint64_t)ecmd->link_mode_masks[1] << 32);
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa = 0;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & MLX5_BITSHIFT(ETHTOOL_LINK_MODE_Autoneg_BIT))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_AUTONEG;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_1000baseT_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_1000baseKX_Full_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_1G;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_10000baseKR_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_10000baseR_FEC_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_10G;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_20000baseMLD2_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_20000baseKR2_Full_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_20G;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseSR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_40000baseLR4_Full_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_40G;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseKR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseCR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseSR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_56000baseLR4_Full_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_56G;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_25000baseCR_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_25000baseKR_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_25000baseSR_Full_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_25G;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_50000baseCR2_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_50000baseKR2_Full_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_50G;
|
2017-11-10 14:18:04 +00:00
|
|
|
if (sc & (MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseSR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT) |
|
|
|
|
MLX5_BITSHIFT(ETHTOOL_LINK_MODE_100000baseLR4_ER4_Full_BIT)))
|
2016-10-26 09:44:02 +00:00
|
|
|
priv->link_speed_capa |= ETH_LINK_SPEED_100G;
|
2017-08-30 14:47:06 +00:00
|
|
|
dev_link.link_duplex = ((ecmd->duplex == DUPLEX_HALF) ?
|
2016-10-26 09:44:02 +00:00
|
|
|
ETH_LINK_HALF_DUPLEX : ETH_LINK_FULL_DUPLEX);
|
|
|
|
dev_link.link_autoneg = !(dev->data->dev_conf.link_speeds &
|
|
|
|
ETH_LINK_SPEED_FIXED);
|
2018-03-12 13:43:19 +00:00
|
|
|
if ((dev_link.link_speed && !dev_link.link_status) ||
|
|
|
|
(!dev_link.link_speed && dev_link.link_status)) {
|
|
|
|
rte_errno = EAGAIN;
|
|
|
|
return -rte_errno;
|
2016-10-26 09:44:02 +00:00
|
|
|
}
|
2018-03-12 13:43:19 +00:00
|
|
|
*link = dev_link;
|
|
|
|
return 0;
|
2016-10-26 09:44:02 +00:00
|
|
|
}
|
|
|
|
|
2018-01-17 17:44:13 +00:00
|
|
|
/**
|
|
|
|
* DPDK callback to retrieve physical link information.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
* @param wait_to_complete
|
2018-03-12 13:43:19 +00:00
|
|
|
* Wait for request completion.
|
2018-03-05 12:21:01 +00:00
|
|
|
*
|
|
|
|
* @return
|
2018-03-12 13:43:19 +00:00
|
|
|
* 0 if link status was not updated, positive if it was, a negative errno
|
|
|
|
* value otherwise and rte_errno is set.
|
2018-01-17 17:44:13 +00:00
|
|
|
*/
|
|
|
|
int
|
2018-03-12 13:43:19 +00:00
|
|
|
mlx5_link_update(struct rte_eth_dev *dev, int wait_to_complete)
|
2018-01-17 17:44:13 +00:00
|
|
|
{
|
|
|
|
int ret;
|
2018-03-12 13:43:19 +00:00
|
|
|
struct rte_eth_link dev_link;
|
|
|
|
time_t start_time = time(NULL);
|
2018-01-17 17:44:13 +00:00
|
|
|
|
2018-03-12 13:43:19 +00:00
|
|
|
do {
|
2018-05-01 09:58:48 +00:00
|
|
|
ret = mlx5_link_update_unlocked_gs(dev, &dev_link);
|
2018-03-12 13:43:19 +00:00
|
|
|
if (ret)
|
2018-05-01 09:58:48 +00:00
|
|
|
ret = mlx5_link_update_unlocked_gset(dev, &dev_link);
|
2018-03-12 13:43:19 +00:00
|
|
|
if (ret == 0)
|
|
|
|
break;
|
|
|
|
/* Handle wait to complete situation. */
|
|
|
|
if (wait_to_complete && ret == -EAGAIN) {
|
|
|
|
if (abs((int)difftime(time(NULL), start_time)) <
|
|
|
|
MLX5_LINK_STATUS_TIMEOUT) {
|
|
|
|
usleep(0);
|
|
|
|
continue;
|
|
|
|
} else {
|
|
|
|
rte_errno = EBUSY;
|
|
|
|
return -rte_errno;
|
|
|
|
}
|
|
|
|
} else if (ret < 0) {
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
} while (wait_to_complete);
|
|
|
|
ret = !!memcmp(&dev->data->dev_link, &dev_link,
|
|
|
|
sizeof(struct rte_eth_link));
|
|
|
|
dev->data->dev_link = dev_link;
|
|
|
|
return ret;
|
2016-10-26 09:44:02 +00:00
|
|
|
}
|
|
|
|
|
2015-10-30 18:52:35 +00:00
|
|
|
/**
|
|
|
|
* DPDK callback to change the MTU.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
* @param in_mtu
|
|
|
|
* New MTU.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:35 +00:00
|
|
|
*/
|
|
|
|
int
|
|
|
|
mlx5_dev_set_mtu(struct rte_eth_dev *dev, uint16_t mtu)
|
|
|
|
{
|
|
|
|
struct priv *priv = dev->data->dev_private;
|
2018-03-05 12:21:06 +00:00
|
|
|
uint16_t kern_mtu = 0;
|
|
|
|
int ret;
|
2015-10-30 18:52:35 +00:00
|
|
|
|
2018-03-05 12:21:04 +00:00
|
|
|
ret = mlx5_get_mtu(dev, &kern_mtu);
|
2017-08-03 09:31:27 +00:00
|
|
|
if (ret)
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2015-10-30 18:52:35 +00:00
|
|
|
/* Set kernel interface MTU first. */
|
2018-03-05 12:21:04 +00:00
|
|
|
ret = mlx5_set_mtu(dev, mtu);
|
2017-08-03 09:31:27 +00:00
|
|
|
if (ret)
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2018-03-05 12:21:04 +00:00
|
|
|
ret = mlx5_get_mtu(dev, &kern_mtu);
|
2017-08-03 09:31:27 +00:00
|
|
|
if (ret)
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2017-08-03 09:31:27 +00:00
|
|
|
if (kern_mtu == mtu) {
|
|
|
|
priv->mtu = mtu;
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(DEBUG, "port %u adapter MTU set to %u",
|
|
|
|
dev->data->port_id, mtu);
|
2018-03-05 12:21:06 +00:00
|
|
|
return 0;
|
2015-10-30 18:52:35 +00:00
|
|
|
}
|
2018-03-05 12:21:06 +00:00
|
|
|
rte_errno = EAGAIN;
|
|
|
|
return -rte_errno;
|
2015-10-30 18:52:35 +00:00
|
|
|
}
|
|
|
|
|
2015-10-30 18:52:39 +00:00
|
|
|
/**
|
|
|
|
* DPDK callback to get flow control status.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
* @param[out] fc_conf
|
|
|
|
* Flow control output buffer.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:39 +00:00
|
|
|
*/
|
|
|
|
int
|
|
|
|
mlx5_dev_get_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
|
|
|
|
{
|
|
|
|
struct ifreq ifr;
|
|
|
|
struct ethtool_pauseparam ethpause = {
|
|
|
|
.cmd = ETHTOOL_GPAUSEPARAM
|
|
|
|
};
|
|
|
|
int ret;
|
|
|
|
|
2016-06-20 13:31:46 +00:00
|
|
|
ifr.ifr_data = (void *)ðpause;
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(WARNING,
|
|
|
|
"port %u ioctl(SIOCETHTOOL, ETHTOOL_GPAUSEPARAM) failed:"
|
|
|
|
" %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2015-10-30 18:52:39 +00:00
|
|
|
}
|
|
|
|
fc_conf->autoneg = ethpause.autoneg;
|
|
|
|
if (ethpause.rx_pause && ethpause.tx_pause)
|
|
|
|
fc_conf->mode = RTE_FC_FULL;
|
|
|
|
else if (ethpause.rx_pause)
|
|
|
|
fc_conf->mode = RTE_FC_RX_PAUSE;
|
|
|
|
else if (ethpause.tx_pause)
|
|
|
|
fc_conf->mode = RTE_FC_TX_PAUSE;
|
|
|
|
else
|
|
|
|
fc_conf->mode = RTE_FC_NONE;
|
2018-03-05 12:21:06 +00:00
|
|
|
return 0;
|
2015-10-30 18:52:39 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* DPDK callback to modify flow control parameters.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
* @param[in] fc_conf
|
|
|
|
* Flow control parameters.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:39 +00:00
|
|
|
*/
|
|
|
|
int
|
|
|
|
mlx5_dev_set_flow_ctrl(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
|
|
|
|
{
|
|
|
|
struct ifreq ifr;
|
|
|
|
struct ethtool_pauseparam ethpause = {
|
|
|
|
.cmd = ETHTOOL_SPAUSEPARAM
|
|
|
|
};
|
|
|
|
int ret;
|
|
|
|
|
2016-06-20 13:31:46 +00:00
|
|
|
ifr.ifr_data = (void *)ðpause;
|
2015-10-30 18:52:39 +00:00
|
|
|
ethpause.autoneg = fc_conf->autoneg;
|
|
|
|
if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
|
|
|
|
(fc_conf->mode & RTE_FC_RX_PAUSE))
|
|
|
|
ethpause.rx_pause = 1;
|
|
|
|
else
|
|
|
|
ethpause.rx_pause = 0;
|
|
|
|
|
|
|
|
if (((fc_conf->mode & RTE_FC_FULL) == RTE_FC_FULL) ||
|
|
|
|
(fc_conf->mode & RTE_FC_TX_PAUSE))
|
|
|
|
ethpause.tx_pause = 1;
|
|
|
|
else
|
|
|
|
ethpause.tx_pause = 0;
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_ifreq(dev, SIOCETHTOOL, &ifr);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(WARNING,
|
|
|
|
"port %u ioctl(SIOCETHTOOL, ETHTOOL_SPAUSEPARAM)"
|
|
|
|
" failed: %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
return ret;
|
2015-10-30 18:52:39 +00:00
|
|
|
}
|
2018-03-05 12:21:06 +00:00
|
|
|
return 0;
|
2015-10-30 18:52:39 +00:00
|
|
|
}
|
|
|
|
|
2015-10-30 18:52:30 +00:00
|
|
|
/**
|
|
|
|
* Get PCI information from struct ibv_device.
|
|
|
|
*
|
|
|
|
* @param device
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
* @param[out] pci_addr
|
|
|
|
* PCI bus address output buffer.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2015-10-30 18:52:30 +00:00
|
|
|
*/
|
|
|
|
int
|
|
|
|
mlx5_ibv_device_to_pci_addr(const struct ibv_device *device,
|
|
|
|
struct rte_pci_addr *pci_addr)
|
|
|
|
{
|
|
|
|
FILE *file;
|
|
|
|
char line[32];
|
|
|
|
MKSTR(path, "%s/device/uevent", device->ibdev_path);
|
|
|
|
|
|
|
|
file = fopen(path, "rb");
|
2018-03-05 12:21:06 +00:00
|
|
|
if (file == NULL) {
|
|
|
|
rte_errno = errno;
|
|
|
|
return -rte_errno;
|
|
|
|
}
|
2015-10-30 18:52:30 +00:00
|
|
|
while (fgets(line, sizeof(line), file) == line) {
|
|
|
|
size_t len = strlen(line);
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
/* Truncate long lines. */
|
|
|
|
if (len == (sizeof(line) - 1))
|
|
|
|
while (line[(len - 1)] != '\n') {
|
|
|
|
ret = fgetc(file);
|
|
|
|
if (ret == EOF)
|
|
|
|
break;
|
|
|
|
line[(len - 1)] = ret;
|
|
|
|
}
|
|
|
|
/* Extract information. */
|
|
|
|
if (sscanf(line,
|
|
|
|
"PCI_SLOT_NAME="
|
2017-07-05 16:55:32 +00:00
|
|
|
"%" SCNx32 ":%" SCNx8 ":%" SCNx8 ".%" SCNx8 "\n",
|
2015-10-30 18:52:30 +00:00
|
|
|
&pci_addr->domain,
|
|
|
|
&pci_addr->bus,
|
|
|
|
&pci_addr->devid,
|
|
|
|
&pci_addr->function) == 4) {
|
|
|
|
ret = 0;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
fclose(file);
|
|
|
|
return 0;
|
|
|
|
}
|
2015-10-30 18:57:23 +00:00
|
|
|
|
2017-09-06 15:03:57 +00:00
|
|
|
/**
|
|
|
|
* Device status handler.
|
|
|
|
*
|
2018-03-05 12:21:04 +00:00
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device.
|
2017-09-06 15:03:57 +00:00
|
|
|
* @param events
|
|
|
|
* Pointer to event flags holder.
|
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* Events bitmap of callback process which can be called immediately.
|
|
|
|
*/
|
|
|
|
static uint32_t
|
2018-03-05 12:21:04 +00:00
|
|
|
mlx5_dev_status_handler(struct rte_eth_dev *dev)
|
2015-10-30 18:57:23 +00:00
|
|
|
{
|
2018-03-05 12:21:04 +00:00
|
|
|
struct priv *priv = dev->data->dev_private;
|
2015-10-30 18:57:23 +00:00
|
|
|
struct ibv_async_event event;
|
2017-09-06 15:03:57 +00:00
|
|
|
uint32_t ret = 0;
|
2015-10-30 18:57:23 +00:00
|
|
|
|
2018-03-12 13:43:19 +00:00
|
|
|
if (mlx5_link_update(dev, 0) == -EAGAIN) {
|
|
|
|
usleep(0);
|
|
|
|
return 0;
|
|
|
|
}
|
2015-10-30 18:57:23 +00:00
|
|
|
/* Read all message and acknowledge them. */
|
|
|
|
for (;;) {
|
2018-01-30 15:34:56 +00:00
|
|
|
if (mlx5_glue->get_async_event(priv->ctx, &event))
|
2015-10-30 18:57:23 +00:00
|
|
|
break;
|
2017-09-06 15:03:57 +00:00
|
|
|
if ((event.event_type == IBV_EVENT_PORT_ACTIVE ||
|
|
|
|
event.event_type == IBV_EVENT_PORT_ERR) &&
|
2018-03-05 12:21:04 +00:00
|
|
|
(dev->data->dev_conf.intr_conf.lsc == 1))
|
2017-09-06 15:03:57 +00:00
|
|
|
ret |= (1 << RTE_ETH_EVENT_INTR_LSC);
|
2017-09-08 10:47:45 +00:00
|
|
|
else if (event.event_type == IBV_EVENT_DEVICE_FATAL &&
|
2018-03-05 12:21:04 +00:00
|
|
|
dev->data->dev_conf.intr_conf.rmv == 1)
|
2017-09-08 10:47:45 +00:00
|
|
|
ret |= (1 << RTE_ETH_EVENT_INTR_RMV);
|
2017-09-06 15:03:57 +00:00
|
|
|
else
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(DEBUG,
|
|
|
|
"port %u event type %d on not handled",
|
|
|
|
dev->data->port_id, event.event_type);
|
2018-01-30 15:34:56 +00:00
|
|
|
mlx5_glue->ack_async_event(&event);
|
2015-10-30 18:57:23 +00:00
|
|
|
}
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Handle interrupts from the NIC.
|
|
|
|
*
|
|
|
|
* @param[in] intr_handle
|
|
|
|
* Interrupt handler.
|
|
|
|
* @param cb_arg
|
|
|
|
* Callback argument.
|
|
|
|
*/
|
|
|
|
void
|
2017-04-06 12:42:22 +00:00
|
|
|
mlx5_dev_interrupt_handler(void *cb_arg)
|
2015-10-30 18:57:23 +00:00
|
|
|
{
|
|
|
|
struct rte_eth_dev *dev = cb_arg;
|
2017-09-06 15:03:57 +00:00
|
|
|
uint32_t events;
|
2015-10-30 18:57:23 +00:00
|
|
|
|
2018-03-05 12:21:04 +00:00
|
|
|
events = mlx5_dev_status_handler(dev);
|
2017-09-06 15:03:57 +00:00
|
|
|
if (events & (1 << RTE_ETH_EVENT_INTR_LSC))
|
2018-01-04 16:01:08 +00:00
|
|
|
_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL);
|
2017-09-08 10:47:45 +00:00
|
|
|
if (events & (1 << RTE_ETH_EVENT_INTR_RMV))
|
2018-01-04 16:01:08 +00:00
|
|
|
_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RMV, NULL);
|
2015-10-30 18:57:23 +00:00
|
|
|
}
|
|
|
|
|
2017-10-06 15:45:49 +00:00
|
|
|
/**
|
|
|
|
* Handle interrupts from the socket.
|
|
|
|
*
|
|
|
|
* @param cb_arg
|
|
|
|
* Callback argument.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
mlx5_dev_handler_socket(void *cb_arg)
|
|
|
|
{
|
|
|
|
struct rte_eth_dev *dev = cb_arg;
|
|
|
|
|
2018-03-05 12:21:04 +00:00
|
|
|
mlx5_socket_handle(dev);
|
2017-10-06 15:45:49 +00:00
|
|
|
}
|
|
|
|
|
2015-10-30 18:57:23 +00:00
|
|
|
/**
|
|
|
|
* Uninstall interrupt handler.
|
|
|
|
*
|
|
|
|
* @param dev
|
2018-03-05 12:21:04 +00:00
|
|
|
* Pointer to Ethernet device.
|
2015-10-30 18:57:23 +00:00
|
|
|
*/
|
|
|
|
void
|
2018-03-05 12:21:04 +00:00
|
|
|
mlx5_dev_interrupt_handler_uninstall(struct rte_eth_dev *dev)
|
2015-10-30 18:57:23 +00:00
|
|
|
{
|
2018-03-05 12:21:04 +00:00
|
|
|
struct priv *priv = dev->data->dev_private;
|
|
|
|
|
2017-10-06 15:45:49 +00:00
|
|
|
if (dev->data->dev_conf.intr_conf.lsc ||
|
|
|
|
dev->data->dev_conf.intr_conf.rmv)
|
|
|
|
rte_intr_callback_unregister(&priv->intr_handle,
|
|
|
|
mlx5_dev_interrupt_handler, dev);
|
|
|
|
if (priv->primary_socket)
|
|
|
|
rte_intr_callback_unregister(&priv->intr_handle_socket,
|
|
|
|
mlx5_dev_handler_socket, dev);
|
2015-10-30 18:57:23 +00:00
|
|
|
priv->intr_handle.fd = 0;
|
2016-06-14 16:17:24 +00:00
|
|
|
priv->intr_handle.type = RTE_INTR_HANDLE_UNKNOWN;
|
2017-10-06 15:45:49 +00:00
|
|
|
priv->intr_handle_socket.fd = 0;
|
|
|
|
priv->intr_handle_socket.type = RTE_INTR_HANDLE_UNKNOWN;
|
2015-10-30 18:57:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* Install interrupt handler.
|
|
|
|
*
|
|
|
|
* @param dev
|
2018-03-05 12:21:04 +00:00
|
|
|
* Pointer to Ethernet device.
|
2015-10-30 18:57:23 +00:00
|
|
|
*/
|
|
|
|
void
|
2018-03-05 12:21:04 +00:00
|
|
|
mlx5_dev_interrupt_handler_install(struct rte_eth_dev *dev)
|
2015-10-30 18:57:23 +00:00
|
|
|
{
|
2018-03-05 12:21:04 +00:00
|
|
|
struct priv *priv = dev->data->dev_private;
|
2018-03-05 12:21:06 +00:00
|
|
|
int ret;
|
|
|
|
int flags;
|
2015-10-30 18:57:23 +00:00
|
|
|
|
|
|
|
assert(priv->ctx->async_fd > 0);
|
|
|
|
flags = fcntl(priv->ctx->async_fd, F_GETFL);
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = fcntl(priv->ctx->async_fd, F_SETFL, flags | O_NONBLOCK);
|
|
|
|
if (ret) {
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(INFO,
|
|
|
|
"port %u failed to change file descriptor async event"
|
|
|
|
" queue",
|
|
|
|
dev->data->port_id);
|
2015-10-30 18:57:23 +00:00
|
|
|
dev->data->dev_conf.intr_conf.lsc = 0;
|
2017-09-08 10:47:45 +00:00
|
|
|
dev->data->dev_conf.intr_conf.rmv = 0;
|
2017-10-06 15:45:49 +00:00
|
|
|
}
|
|
|
|
if (dev->data->dev_conf.intr_conf.lsc ||
|
|
|
|
dev->data->dev_conf.intr_conf.rmv) {
|
2015-10-30 18:57:23 +00:00
|
|
|
priv->intr_handle.fd = priv->ctx->async_fd;
|
|
|
|
priv->intr_handle.type = RTE_INTR_HANDLE_EXT;
|
|
|
|
rte_intr_callback_register(&priv->intr_handle,
|
2017-10-06 15:45:49 +00:00
|
|
|
mlx5_dev_interrupt_handler, dev);
|
|
|
|
}
|
2018-03-05 12:21:06 +00:00
|
|
|
ret = mlx5_socket_init(dev);
|
|
|
|
if (ret)
|
2018-03-13 09:23:56 +00:00
|
|
|
DRV_LOG(ERR, "port %u cannot initialise socket: %s",
|
|
|
|
dev->data->port_id, strerror(rte_errno));
|
2018-03-05 12:21:06 +00:00
|
|
|
else if (priv->primary_socket) {
|
2017-10-06 15:45:49 +00:00
|
|
|
priv->intr_handle_socket.fd = priv->primary_socket;
|
|
|
|
priv->intr_handle_socket.type = RTE_INTR_HANDLE_EXT;
|
|
|
|
rte_intr_callback_register(&priv->intr_handle_socket,
|
|
|
|
mlx5_dev_handler_socket, dev);
|
2015-10-30 18:57:23 +00:00
|
|
|
}
|
|
|
|
}
|
2016-03-17 15:38:54 +00:00
|
|
|
|
|
|
|
/**
|
|
|
|
* DPDK callback to bring the link DOWN.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2016-03-17 15:38:54 +00:00
|
|
|
*/
|
|
|
|
int
|
|
|
|
mlx5_set_link_down(struct rte_eth_dev *dev)
|
|
|
|
{
|
2018-03-05 12:21:04 +00:00
|
|
|
return mlx5_set_flags(dev, ~IFF_UP, ~IFF_UP);
|
2016-03-17 15:38:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* DPDK callback to bring the link UP.
|
|
|
|
*
|
|
|
|
* @param dev
|
|
|
|
* Pointer to Ethernet device structure.
|
|
|
|
*
|
|
|
|
* @return
|
2018-03-05 12:21:06 +00:00
|
|
|
* 0 on success, a negative errno value otherwise and rte_errno is set.
|
2016-03-17 15:38:54 +00:00
|
|
|
*/
|
|
|
|
int
|
|
|
|
mlx5_set_link_up(struct rte_eth_dev *dev)
|
|
|
|
{
|
2018-03-05 12:21:04 +00:00
|
|
|
return mlx5_set_flags(dev, ~IFF_UP, IFF_UP);
|
2016-03-17 15:38:54 +00:00
|
|
|
}
|
2016-03-17 15:38:55 +00:00
|
|
|
|
2016-06-24 13:17:51 +00:00
|
|
|
/**
|
|
|
|
* Configure the TX function to use.
|
|
|
|
*
|
2017-10-06 15:45:48 +00:00
|
|
|
* @param dev
|
2018-03-05 12:21:04 +00:00
|
|
|
* Pointer to private data structure.
|
2018-01-10 09:16:57 +00:00
|
|
|
*
|
|
|
|
* @return
|
|
|
|
* Pointer to selected Tx burst function.
|
2016-06-24 13:17:51 +00:00
|
|
|
*/
|
2018-01-10 09:16:57 +00:00
|
|
|
eth_tx_burst_t
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2018-03-05 12:21:04 +00:00
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mlx5_select_tx_function(struct rte_eth_dev *dev)
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2016-06-24 13:17:51 +00:00
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{
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2018-03-05 12:21:04 +00:00
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struct priv *priv = dev->data->dev_private;
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2018-01-10 09:16:57 +00:00
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eth_tx_burst_t tx_pkt_burst = mlx5_tx_burst;
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2018-01-10 09:16:58 +00:00
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struct mlx5_dev_config *config = &priv->config;
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2018-01-10 09:17:00 +00:00
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uint64_t tx_offloads = dev->data->dev_conf.txmode.offloads;
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int tso = !!(tx_offloads & (DEV_TX_OFFLOAD_TCP_TSO |
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DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
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2018-05-09 00:14:51 +00:00
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DEV_TX_OFFLOAD_GRE_TNL_TSO |
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DEV_TX_OFFLOAD_IP_TNL_TSO |
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DEV_TX_OFFLOAD_UDP_TNL_TSO));
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2018-04-08 12:41:20 +00:00
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int swp = !!(tx_offloads & (DEV_TX_OFFLOAD_IP_TNL_TSO |
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DEV_TX_OFFLOAD_UDP_TNL_TSO |
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DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM));
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2018-01-10 09:17:00 +00:00
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int vlan_insert = !!(tx_offloads & DEV_TX_OFFLOAD_VLAN_INSERT);
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2018-01-10 09:16:57 +00:00
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2017-10-06 15:45:48 +00:00
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assert(priv != NULL);
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2016-06-24 13:17:57 +00:00
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/* Select appropriate TX function. */
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2018-04-08 12:41:20 +00:00
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if (vlan_insert || tso || swp)
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2018-01-10 09:17:00 +00:00
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return tx_pkt_burst;
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2018-01-10 09:16:58 +00:00
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if (config->mps == MLX5_MPW_ENHANCED) {
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2018-03-05 12:21:04 +00:00
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if (mlx5_check_vec_tx_support(dev) > 0) {
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if (mlx5_check_raw_vec_tx_support(dev) > 0)
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2018-01-10 09:16:57 +00:00
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tx_pkt_burst = mlx5_tx_burst_raw_vec;
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2017-07-06 18:41:10 +00:00
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else
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2018-01-10 09:16:57 +00:00
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tx_pkt_burst = mlx5_tx_burst_vec;
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2018-03-13 09:23:56 +00:00
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DRV_LOG(DEBUG,
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"port %u selected enhanced MPW Tx vectorized"
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" function",
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dev->data->port_id);
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2017-07-06 18:41:10 +00:00
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} else {
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2018-01-10 09:16:57 +00:00
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tx_pkt_burst = mlx5_tx_burst_empw;
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2018-03-13 09:23:56 +00:00
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DRV_LOG(DEBUG,
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"port %u selected enhanced MPW Tx function",
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dev->data->port_id);
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2017-07-06 18:41:10 +00:00
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}
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2018-01-10 09:16:58 +00:00
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} else if (config->mps && (config->txq_inline > 0)) {
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2018-01-10 09:16:57 +00:00
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tx_pkt_burst = mlx5_tx_burst_mpw_inline;
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2018-03-13 09:23:56 +00:00
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DRV_LOG(DEBUG, "port %u selected MPW inline Tx function",
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dev->data->port_id);
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2018-01-10 09:16:58 +00:00
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} else if (config->mps) {
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2018-01-10 09:16:57 +00:00
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tx_pkt_burst = mlx5_tx_burst_mpw;
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2018-03-13 09:23:56 +00:00
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DRV_LOG(DEBUG, "port %u selected MPW Tx function",
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dev->data->port_id);
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2016-06-24 13:17:56 +00:00
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}
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2018-01-10 09:16:57 +00:00
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return tx_pkt_burst;
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2016-06-24 13:17:51 +00:00
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}
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/**
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* Configure the RX function to use.
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*
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2017-10-06 15:45:48 +00:00
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* @param dev
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2018-03-05 12:21:04 +00:00
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* Pointer to private data structure.
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2018-01-10 09:16:57 +00:00
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*
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* @return
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* Pointer to selected Rx burst function.
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2016-06-24 13:17:51 +00:00
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*/
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2018-01-10 09:16:57 +00:00
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eth_rx_burst_t
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2018-03-05 12:21:04 +00:00
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mlx5_select_rx_function(struct rte_eth_dev *dev)
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2016-06-24 13:17:51 +00:00
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{
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2018-01-10 09:16:57 +00:00
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eth_rx_burst_t rx_pkt_burst = mlx5_rx_burst;
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2018-03-05 12:21:04 +00:00
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assert(dev != NULL);
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if (mlx5_check_vec_rx_support(dev) > 0) {
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2018-01-10 09:16:57 +00:00
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rx_pkt_burst = mlx5_rx_burst_vec;
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2018-03-13 09:23:56 +00:00
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DRV_LOG(DEBUG, "port %u selected Rx vectorized function",
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dev->data->port_id);
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2018-05-09 11:13:50 +00:00
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} else if (mlx5_mprq_enabled(dev)) {
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rx_pkt_burst = mlx5_rx_burst_mprq;
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2017-07-06 18:41:10 +00:00
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}
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2018-01-10 09:16:57 +00:00
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return rx_pkt_burst;
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2016-06-24 13:17:51 +00:00
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}
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2018-01-20 21:12:21 +00:00
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/**
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* Check if mlx5 device was removed.
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*
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* @param dev
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* Pointer to Ethernet device structure.
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*
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* @return
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* 1 when device is removed, otherwise 0.
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*/
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int
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mlx5_is_removed(struct rte_eth_dev *dev)
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{
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struct ibv_device_attr device_attr;
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struct priv *priv = dev->data->dev_private;
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2018-01-30 15:34:56 +00:00
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if (mlx5_glue->query_device(priv->ctx, &device_attr) == EIO)
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2018-01-20 21:12:21 +00:00
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return 1;
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return 0;
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}
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