numam-dpdk/config/defconfig_arm64-xgene1-linuxapp-gcc

# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2015 Cavium, Inc
#

#include "defconfig_arm64-armv8a-linuxapp-gcc"

CONFIG_RTE_MACHINE="xgene1"
CONFIG_RTE_CACHE_LINE_SIZE=64
config: use SPDX tag for Cavium copyright files Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Hemant Agrawal <hemant.agrawal@nxp.com> 2018-01-08 05:25:19 +00:00			`# SPDX-License-Identifier: BSD-3-Clause`
			`# Copyright(c) 2015 Cavium, Inc`
mk: add xgene1 machine target based on armv8-a created the new xgene1 machine target to address the difference in optional armv8-a CRC extension availability compared to default armv8-a machine target(enabled CRC extension by default) Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> 2015-11-23 18:45:38 +00:00			`#`

config: use armv8a as base for arm64 targets let each armv8 machine targets capture only the differences between the common defconfig_arm64-armv8a-linuxapp-gcc Suggested-by: Thomas Monjalon <thomas.monjalon@6wind.com> Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> 2015-11-30 17:20:37 +00:00			`#include "defconfig_arm64-armv8a-linuxapp-gcc"`
mk: add xgene1 machine target based on armv8-a created the new xgene1 machine target to address the difference in optional armv8-a CRC extension availability compared to default armv8-a machine target(enabled CRC extension by default) Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> 2015-11-23 18:45:38 +00:00
			`CONFIG_RTE_MACHINE="xgene1"`
config: set cache line as 128B for generic arm64 armv8 implementations may have 64B or 128B cache line. Setting to the maximum available cache line size in generic config to address minimum DMA alignment across all arm64 implementations. Increasing the cacheline size has no negative impact to cache invalidation on systems with a smaller cache line. The need for the minimum DMA alignment has impact on functional aspects of the platform so default config should cater the functional aspects. There is an impact on memory usage with this scheme, but that's not too important for the single image arm64 distribution use case. The arm64 linux kernel followed the similar approach for single arm64 image use case. http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h Signed-off-by: Jerin Jacob <jerin.jacob@caviumnetworks.com> Acked-by: Jianbo Liu <jianbo.liu@linaro.org> Acked-by: Santosh Shukla <santosh.shukla@caviumnetworks.com> 2017-04-26 16:29:19 +00:00			`CONFIG_RTE_CACHE_LINE_SIZE=64`