2012-09-04 12:54:00 +00:00
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/*-
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* BSD LICENSE
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2014-06-03 23:42:50 +00:00
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*
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2014-02-10 11:46:50 +00:00
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* Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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2012-09-04 12:54:00 +00:00
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* All rights reserved.
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2014-06-03 23:42:50 +00:00
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*
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2013-09-18 10:00:00 +00:00
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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2012-09-04 12:54:00 +00:00
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* are met:
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2014-06-03 23:42:50 +00:00
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*
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2013-09-18 10:00:00 +00:00
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* * Redistributions of source code must retain the above copyright
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2012-09-04 12:54:00 +00:00
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* notice, this list of conditions and the following disclaimer.
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2013-09-18 10:00:00 +00:00
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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2012-09-04 12:54:00 +00:00
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* distribution.
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2013-09-18 10:00:00 +00:00
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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2012-09-04 12:54:00 +00:00
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* from this software without specific prior written permission.
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2014-06-03 23:42:50 +00:00
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*
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2013-09-18 10:00:00 +00:00
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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2012-09-04 12:54:00 +00:00
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _IXGBE_ETHDEV_H_
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#define _IXGBE_ETHDEV_H_
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2012-12-19 23:00:00 +00:00
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#include "ixgbe/ixgbe_dcb.h"
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#include "ixgbe/ixgbe_dcb_82599.h"
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#include "ixgbe/ixgbe_dcb_82598.h"
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2013-11-08 02:00:00 +00:00
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#include "ixgbe_bypass.h"
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2012-09-04 12:54:00 +00:00
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/* need update link, bit flag */
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#define IXGBE_FLAG_NEED_LINK_UPDATE (uint32_t)(1 << 0)
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2013-06-03 00:00:00 +00:00
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#define IXGBE_FLAG_MAILBOX (uint32_t)(1 << 1)
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2012-09-04 12:54:00 +00:00
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/*
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* Defines that were not part of ixgbe_type.h as they are not used by the
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* FreeBSD driver.
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*/
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#define IXGBE_ADVTXD_MAC_1588 0x00080000 /* IEEE1588 Timestamp packet */
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#define IXGBE_RXD_STAT_TMST 0x10000 /* Timestamped Packet indication */
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#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* L4 Packet TYPE, resvd */
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#define IXGBE_RXDADV_ERR_CKSUM_BIT 30
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#define IXGBE_RXDADV_ERR_CKSUM_MSK 3
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#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Bit shift for l2_len */
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2012-12-19 23:00:00 +00:00
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#define IXGBE_NB_STAT_MAPPING_REGS 32
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2012-12-19 23:00:00 +00:00
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#define IXGBE_EXTENDED_VLAN (uint32_t)(1 << 26) /* EXTENDED VLAN ENABLE */
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2012-09-04 12:54:00 +00:00
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#define IXGBE_VFTA_SIZE 128
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2013-06-03 00:00:00 +00:00
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#define IXGBE_VLAN_TAG_SIZE 4
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2012-12-24 23:00:00 +00:00
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#define IXGBE_MAX_RX_QUEUE_NUM 128
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#ifndef NBBY
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#define NBBY 8 /* number of bits in a byte */
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#endif
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2012-12-19 23:00:00 +00:00
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#define IXGBE_HWSTRIP_BITMAP_SIZE (IXGBE_MAX_RX_QUEUE_NUM / (sizeof(uint32_t) * NBBY))
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2013-09-26 13:34:44 +00:00
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/* Loopback operation modes */
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/* 82599 specific loopback operation types */
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2014-05-26 07:45:30 +00:00
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#define IXGBE_LPBK_82599_NONE 0x0 /* Default value. Loopback is disabled. */
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#define IXGBE_LPBK_82599_TX_RX 0x1 /* Tx->Rx loopback operation is enabled. */
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2012-09-04 12:54:00 +00:00
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2014-05-26 07:45:30 +00:00
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#define IXGBE_MAX_JUMBO_FRAME_SIZE 0x2600 /* Maximum Jumbo frame size. */
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#define IXGBE_RTTBCNRC_RF_INT_MASK_BASE 0x000003FF
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#define IXGBE_RTTBCNRC_RF_INT_MASK_M \
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(IXGBE_RTTBCNRC_RF_INT_MASK_BASE << IXGBE_RTTBCNRC_RF_INT_SHIFT)
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#define IXGBE_MAX_QUEUE_NUM_PER_VF 8
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2014-06-16 07:31:45 +00:00
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#define IXGBE_SYN_FILTER_ENABLE 0x00000001 /* syn filter enable field */
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#define IXGBE_SYN_FILTER_QUEUE 0x000000FE /* syn filter queue field */
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#define IXGBE_SYN_FILTER_QUEUE_SHIFT 1 /* syn filter queue field shift */
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#define IXGBE_SYN_FILTER_SYNQFP 0x80000000 /* syn filter SYNQFP */
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#define IXGBE_ETQF_UP 0x00070000 /* ethertype filter priority field */
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#define IXGBE_ETQF_SHIFT 16
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#define IXGBE_ETQF_UP_EN 0x00080000
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#define IXGBE_ETQF_ETHERTYPE 0x0000FFFF /* ethertype filter ethertype field */
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#define IXGBE_ETQF_MAX_PRI 7
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#define IXGBE_SDPQF_DSTPORT 0xFFFF0000 /* dst port field */
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#define IXGBE_SDPQF_DSTPORT_SHIFT 16 /* dst port field shift */
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#define IXGBE_SDPQF_SRCPORT 0x0000FFFF /* src port field */
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#define IXGBE_L34T_IMIR_SIZE_BP 0x00001000
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#define IXGBE_L34T_IMIR_RESERVE 0x00080000 /* bit 13 to 19 must be set to 1000000b. */
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#define IXGBE_L34T_IMIR_LLI 0x00100000
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#define IXGBE_L34T_IMIR_QUEUE 0x0FE00000
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#define IXGBE_L34T_IMIR_QUEUE_SHIFT 21
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#define IXGBE_5TUPLE_MAX_PRI 7
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#define IXGBE_5TUPLE_MIN_PRI 1
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2012-09-04 12:54:00 +00:00
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/*
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* Information about the fdir mode.
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*/
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struct ixgbe_hw_fdir_info {
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uint16_t collision;
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uint16_t free;
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uint16_t maxhash;
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uint8_t maxlen;
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uint64_t add;
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uint64_t remove;
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uint64_t f_add;
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uint64_t f_remove;
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};
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/* structure for interrupt relative data */
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struct ixgbe_interrupt {
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uint32_t flags;
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2013-06-03 00:00:00 +00:00
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uint32_t mask;
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2012-09-04 12:54:00 +00:00
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};
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2012-12-19 23:00:00 +00:00
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struct ixgbe_stat_mapping_registers {
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uint32_t tqsm[IXGBE_NB_STAT_MAPPING_REGS];
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uint32_t rqsmr[IXGBE_NB_STAT_MAPPING_REGS];
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};
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2012-09-04 12:54:00 +00:00
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struct ixgbe_vfta {
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uint32_t vfta[IXGBE_VFTA_SIZE];
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};
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2012-12-19 23:00:00 +00:00
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struct ixgbe_hwstrip {
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uint32_t bitmap[IXGBE_HWSTRIP_BITMAP_SIZE];
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};
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2013-06-03 00:00:00 +00:00
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/*
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* VF data which used by PF host only
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*/
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#define IXGBE_MAX_VF_MC_ENTRIES 30
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2013-09-18 10:00:00 +00:00
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#define IXGBE_MAX_MR_RULE_ENTRIES 4 /* number of mirroring rules supported */
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2014-06-03 23:42:50 +00:00
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#define IXGBE_MAX_UTA 128
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2013-09-18 10:00:00 +00:00
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struct ixgbe_uta_info {
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uint8_t uc_filter_type;
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uint16_t uta_in_use;
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uint32_t uta_shadow[IXGBE_MAX_UTA];
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};
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struct ixgbe_mirror_info {
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2014-06-03 23:42:50 +00:00
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struct rte_eth_vmdq_mirror_conf mr_conf[ETH_VMDQ_NUM_MIRROR_RULE];
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2013-09-18 10:00:00 +00:00
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/**< store PF mirror rules configuration*/
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};
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2013-06-03 00:00:00 +00:00
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struct ixgbe_vf_info {
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uint8_t vf_mac_addresses[ETHER_ADDR_LEN];
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uint16_t vf_mc_hashes[IXGBE_MAX_VF_MC_ENTRIES];
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uint16_t num_vf_mc_hashes;
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uint16_t default_vf_vlan_id;
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uint16_t vlans_enabled;
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bool clear_to_send;
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2014-05-26 07:45:30 +00:00
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uint16_t tx_rate[IXGBE_MAX_QUEUE_NUM_PER_VF];
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2013-06-03 00:00:00 +00:00
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uint16_t vlan_count;
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uint8_t spoofchk_enabled;
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2015-01-12 05:59:08 +00:00
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uint8_t api_version;
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2013-06-03 00:00:00 +00:00
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};
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2015-01-12 07:16:10 +00:00
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/*
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* Structure to store filters' info.
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*/
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struct ixgbe_filter_info {
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uint8_t ethertype_mask; /* Bit mask for every used ethertype filter */
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/* store used ethertype filters*/
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uint16_t ethertype_filters[IXGBE_MAX_ETQF_FILTERS];
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};
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2012-09-04 12:54:00 +00:00
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/*
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* Structure to store private data for each driver instance (for each port).
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*/
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struct ixgbe_adapter {
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struct ixgbe_hw hw;
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struct ixgbe_hw_stats stats;
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struct ixgbe_hw_fdir_info fdir;
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struct ixgbe_interrupt intr;
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2012-12-19 23:00:00 +00:00
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struct ixgbe_stat_mapping_registers stat_mappings;
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2012-09-04 12:54:00 +00:00
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struct ixgbe_vfta shadow_vfta;
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2012-12-19 23:00:00 +00:00
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struct ixgbe_hwstrip hwstrip;
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2012-12-19 23:00:00 +00:00
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struct ixgbe_dcb_config dcb_config;
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2013-09-18 10:00:00 +00:00
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struct ixgbe_mirror_info mr_data;
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2013-06-03 00:00:00 +00:00
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struct ixgbe_vf_info *vfdata;
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2013-09-18 10:00:00 +00:00
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struct ixgbe_uta_info uta_info;
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2013-11-08 02:00:00 +00:00
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#ifdef RTE_NIC_BYPASS
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struct ixgbe_bypass_info bps;
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#endif /* RTE_NIC_BYPASS */
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2015-01-12 07:16:10 +00:00
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struct ixgbe_filter_info filter;
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2012-09-04 12:54:00 +00:00
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};
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2014-06-16 07:31:45 +00:00
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/*
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* Possible l4type of 5tuple filters.
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*/
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enum ixgbe_5tuple_protocol {
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IXGBE_FILTER_PROTOCOL_TCP = 0,
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IXGBE_FILTER_PROTOCOL_UDP,
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IXGBE_FILTER_PROTOCOL_SCTP,
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IXGBE_FILTER_PROTOCOL_NONE,
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};
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2012-09-04 12:54:00 +00:00
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#define IXGBE_DEV_PRIVATE_TO_HW(adapter)\
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(&((struct ixgbe_adapter *)adapter)->hw)
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#define IXGBE_DEV_PRIVATE_TO_STATS(adapter) \
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(&((struct ixgbe_adapter *)adapter)->stats)
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#define IXGBE_DEV_PRIVATE_TO_INTR(adapter) \
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(&((struct ixgbe_adapter *)adapter)->intr)
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#define IXGBE_DEV_PRIVATE_TO_FDIR_INFO(adapter) \
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(&((struct ixgbe_adapter *)adapter)->fdir)
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2012-12-19 23:00:00 +00:00
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#define IXGBE_DEV_PRIVATE_TO_STAT_MAPPINGS(adapter) \
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(&((struct ixgbe_adapter *)adapter)->stat_mappings)
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2012-09-04 12:54:00 +00:00
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#define IXGBE_DEV_PRIVATE_TO_VFTA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->shadow_vfta)
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2012-12-19 23:00:00 +00:00
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#define IXGBE_DEV_PRIVATE_TO_HWSTRIP_BITMAP(adapter) \
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(&((struct ixgbe_adapter *)adapter)->hwstrip)
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2012-09-04 12:54:00 +00:00
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2012-12-19 23:00:00 +00:00
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#define IXGBE_DEV_PRIVATE_TO_DCB_CFG(adapter) \
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(&((struct ixgbe_adapter *)adapter)->dcb_config)
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2013-06-03 00:00:00 +00:00
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#define IXGBE_DEV_PRIVATE_TO_P_VFDATA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->vfdata)
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2013-09-18 10:00:00 +00:00
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#define IXGBE_DEV_PRIVATE_TO_PFDATA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->mr_data)
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#define IXGBE_DEV_PRIVATE_TO_UTA(adapter) \
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(&((struct ixgbe_adapter *)adapter)->uta_info)
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2015-01-12 07:16:10 +00:00
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#define IXGBE_DEV_PRIVATE_TO_FILTER_INFO(adapter) \
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(&((struct ixgbe_adapter *)adapter)->filter)
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2012-09-04 12:54:00 +00:00
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/*
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* RX/TX function prototypes
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*/
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void ixgbe_dev_clear_queues(struct rte_eth_dev *dev);
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2012-12-19 23:00:00 +00:00
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void ixgbe_dev_rx_queue_release(void *rxq);
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2012-09-04 12:54:00 +00:00
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2012-12-19 23:00:00 +00:00
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void ixgbe_dev_tx_queue_release(void *txq);
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2012-09-04 12:54:00 +00:00
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int ixgbe_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t rx_queue_id,
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uint16_t nb_rx_desc, unsigned int socket_id,
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const struct rte_eth_rxconf *rx_conf,
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struct rte_mempool *mb_pool);
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int ixgbe_dev_tx_queue_setup(struct rte_eth_dev *dev, uint16_t tx_queue_id,
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uint16_t nb_tx_desc, unsigned int socket_id,
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const struct rte_eth_txconf *tx_conf);
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2014-06-03 23:42:50 +00:00
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uint32_t ixgbe_dev_rx_queue_count(struct rte_eth_dev *dev,
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2013-06-03 00:00:00 +00:00
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uint16_t rx_queue_id);
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2013-07-22 22:00:00 +00:00
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int ixgbe_dev_rx_descriptor_done(void *rx_queue, uint16_t offset);
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2012-09-04 12:54:00 +00:00
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int ixgbe_dev_rx_init(struct rte_eth_dev *dev);
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void ixgbe_dev_tx_init(struct rte_eth_dev *dev);
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2015-01-27 12:16:18 +00:00
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int ixgbe_dev_rxtx_start(struct rte_eth_dev *dev);
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2012-09-04 12:54:00 +00:00
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2014-05-28 08:06:37 +00:00
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int ixgbe_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ixgbe_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id);
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int ixgbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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int ixgbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);
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2012-09-04 12:54:00 +00:00
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int ixgbevf_dev_rx_init(struct rte_eth_dev *dev);
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void ixgbevf_dev_tx_init(struct rte_eth_dev *dev);
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void ixgbevf_dev_rxtx_start(struct rte_eth_dev *dev);
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2012-12-19 23:00:00 +00:00
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uint16_t ixgbe_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
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2012-09-04 12:54:00 +00:00
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uint16_t nb_pkts);
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2012-12-19 23:00:00 +00:00
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#ifdef RTE_LIBRTE_IXGBE_RX_ALLOW_BULK_ALLOC
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uint16_t ixgbe_recv_pkts_bulk_alloc(void *rx_queue, struct rte_mbuf **rx_pkts,
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uint16_t nb_pkts);
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#endif
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2012-12-19 23:00:00 +00:00
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uint16_t ixgbe_recv_scattered_pkts(void *rx_queue,
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2012-09-04 12:54:00 +00:00
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struct rte_mbuf **rx_pkts, uint16_t nb_pkts);
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2012-12-19 23:00:00 +00:00
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uint16_t ixgbe_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,
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uint16_t nb_pkts);
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uint16_t ixgbe_xmit_pkts_simple(void *tx_queue, struct rte_mbuf **tx_pkts,
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2012-09-04 12:54:00 +00:00
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uint16_t nb_pkts);
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2014-05-16 08:58:40 +00:00
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int ixgbe_dev_rss_hash_update(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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2014-05-16 08:58:42 +00:00
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int ixgbe_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
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struct rte_eth_rss_conf *rss_conf);
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2012-09-04 12:54:00 +00:00
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/*
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* Flow director function prototypes
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*/
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int ixgbe_fdir_configure(struct rte_eth_dev *dev);
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int ixgbe_fdir_add_signature_filter(struct rte_eth_dev *dev,
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struct rte_fdir_filter *fdir_filter, uint8_t queue);
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int ixgbe_fdir_update_signature_filter(struct rte_eth_dev *dev,
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struct rte_fdir_filter *fdir_filter, uint8_t queue);
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int ixgbe_fdir_remove_signature_filter(struct rte_eth_dev *dev,
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struct rte_fdir_filter *fdir_filter);
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void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
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struct rte_eth_fdir *fdir);
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int ixgbe_fdir_add_perfect_filter(struct rte_eth_dev *dev,
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struct rte_fdir_filter *fdir_filter, uint16_t soft_id,
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uint8_t queue, uint8_t drop);
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int ixgbe_fdir_update_perfect_filter(struct rte_eth_dev *dev,
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struct rte_fdir_filter *fdir_filter,uint16_t soft_id,
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uint8_t queue, uint8_t drop);
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int ixgbe_fdir_remove_perfect_filter(struct rte_eth_dev *dev,
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struct rte_fdir_filter *fdir_filter, uint16_t soft_id);
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int ixgbe_fdir_set_masks(struct rte_eth_dev *dev,
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struct rte_fdir_masks *fdir_masks);
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2012-12-19 23:00:00 +00:00
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void ixgbe_configure_dcb(struct rte_eth_dev *dev);
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2013-06-03 00:00:00 +00:00
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/*
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* misc function prototypes
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*/
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void ixgbe_vlan_hw_filter_enable(struct rte_eth_dev *dev);
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void ixgbe_vlan_hw_filter_disable(struct rte_eth_dev *dev);
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void ixgbe_vlan_hw_strip_enable_all(struct rte_eth_dev *dev);
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void ixgbe_vlan_hw_strip_disable_all(struct rte_eth_dev *dev);
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void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev);
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void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev);
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int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev);
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2014-11-08 04:26:14 +00:00
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uint32_t ixgbe_convert_vm_rx_mask_to_val(uint16_t rx_mask, uint32_t orig_val);
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2012-09-04 12:54:00 +00:00
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#endif /* _IXGBE_ETHDEV_H_ */
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