examples/l3fwd-power: add high/regular perf cores options
Added high/regular performance core pinning configuration options
that can be used in place of the existing 'config' option.
'--high-perf-cores CORELIST' option allow the user to specify a
high performance cores list; if this option is not used and the
'perf-config' option is used, the application will query the
system using the rte_power library in order to get a list of
available high performance cores. The cores that are considered
high performance are the cores that have turbo enabled.
'--perf-config (port,queue,hi_perf,lcore_index)'
option is similar to the existing config option, the cores are specified
as indices for bins containing high or regular performance cores.
Example:
l3fwd-power -l 6,7 -- -p 0xff \
--high-perf-cores 6 --perf-config="(0,0,0,0),(1,0,1,0)"
cores 6 and 7 are used, core 6 is specified as a high performance core.
port 0 queue 0 will use a regular performance core, index 0 (core 7)
port 1 queue 0 will use a high performance core, index 0 (core 6)
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>
2018-06-11 10:03:23 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(c) 2010-2018 Intel Corporation
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*/
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#include <stdio.h>
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#include <string.h>
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#include <rte_common.h>
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#include <rte_memory.h>
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#include <rte_lcore.h>
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#include <rte_power.h>
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#include <rte_string_fns.h>
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#include "perf_core.h"
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#include "main.h"
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static uint16_t hp_lcores[RTE_MAX_LCORE];
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static uint16_t nb_hp_lcores;
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struct perf_lcore_params {
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uint16_t port_id;
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uint8_t queue_id;
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uint8_t high_perf;
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uint8_t lcore_idx;
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} __rte_cache_aligned;
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static struct perf_lcore_params prf_lc_prms[MAX_LCORE_PARAMS];
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static uint16_t nb_prf_lc_prms;
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2020-07-14 10:30:02 +00:00
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static int
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is_hp_core(unsigned int lcore)
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{
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struct rte_power_core_capabilities caps;
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int ret;
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/* do we have power management enabled? */
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if (rte_power_get_env() == PM_ENV_NOT_SET) {
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/* there's no power management, so just mark it as high perf */
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return 1;
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}
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ret = rte_power_get_capabilities(lcore, &caps);
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return ret == 0 && caps.turbo;
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}
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examples/l3fwd-power: add high/regular perf cores options
Added high/regular performance core pinning configuration options
that can be used in place of the existing 'config' option.
'--high-perf-cores CORELIST' option allow the user to specify a
high performance cores list; if this option is not used and the
'perf-config' option is used, the application will query the
system using the rte_power library in order to get a list of
available high performance cores. The cores that are considered
high performance are the cores that have turbo enabled.
'--perf-config (port,queue,hi_perf,lcore_index)'
option is similar to the existing config option, the cores are specified
as indices for bins containing high or regular performance cores.
Example:
l3fwd-power -l 6,7 -- -p 0xff \
--high-perf-cores 6 --perf-config="(0,0,0,0),(1,0,1,0)"
cores 6 and 7 are used, core 6 is specified as a high performance core.
port 0 queue 0 will use a regular performance core, index 0 (core 7)
port 1 queue 0 will use a high performance core, index 0 (core 6)
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>
2018-06-11 10:03:23 +00:00
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int
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update_lcore_params(void)
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{
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uint8_t non_perf_lcores[RTE_MAX_LCORE];
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uint16_t nb_non_perf_lcores = 0;
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2020-07-14 10:30:02 +00:00
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int i, j;
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examples/l3fwd-power: add high/regular perf cores options
Added high/regular performance core pinning configuration options
that can be used in place of the existing 'config' option.
'--high-perf-cores CORELIST' option allow the user to specify a
high performance cores list; if this option is not used and the
'perf-config' option is used, the application will query the
system using the rte_power library in order to get a list of
available high performance cores. The cores that are considered
high performance are the cores that have turbo enabled.
'--perf-config (port,queue,hi_perf,lcore_index)'
option is similar to the existing config option, the cores are specified
as indices for bins containing high or regular performance cores.
Example:
l3fwd-power -l 6,7 -- -p 0xff \
--high-perf-cores 6 --perf-config="(0,0,0,0),(1,0,1,0)"
cores 6 and 7 are used, core 6 is specified as a high performance core.
port 0 queue 0 will use a regular performance core, index 0 (core 7)
port 1 queue 0 will use a high performance core, index 0 (core 6)
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>
2018-06-11 10:03:23 +00:00
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/* if perf-config option was not used do nothing */
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if (nb_prf_lc_prms == 0)
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return 0;
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/* if high-perf-cores option was not used query every available core */
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if (nb_hp_lcores == 0) {
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for (i = 0; i < RTE_MAX_LCORE; i++) {
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2020-07-14 10:30:02 +00:00
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if (rte_lcore_is_enabled(i) && is_hp_core(i)) {
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hp_lcores[nb_hp_lcores] = i;
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nb_hp_lcores++;
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examples/l3fwd-power: add high/regular perf cores options
Added high/regular performance core pinning configuration options
that can be used in place of the existing 'config' option.
'--high-perf-cores CORELIST' option allow the user to specify a
high performance cores list; if this option is not used and the
'perf-config' option is used, the application will query the
system using the rte_power library in order to get a list of
available high performance cores. The cores that are considered
high performance are the cores that have turbo enabled.
'--perf-config (port,queue,hi_perf,lcore_index)'
option is similar to the existing config option, the cores are specified
as indices for bins containing high or regular performance cores.
Example:
l3fwd-power -l 6,7 -- -p 0xff \
--high-perf-cores 6 --perf-config="(0,0,0,0),(1,0,1,0)"
cores 6 and 7 are used, core 6 is specified as a high performance core.
port 0 queue 0 will use a regular performance core, index 0 (core 7)
port 1 queue 0 will use a high performance core, index 0 (core 6)
Signed-off-by: Radu Nicolau <radu.nicolau@intel.com>
Acked-by: David Hunt <david.hunt@intel.com>
2018-06-11 10:03:23 +00:00
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}
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}
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}
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/* create a list on non high performance cores*/
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for (i = 0; i < RTE_MAX_LCORE; i++) {
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if (rte_lcore_is_enabled(i)) {
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int hp = 0;
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for (j = 0; j < nb_hp_lcores; j++) {
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if (hp_lcores[j] == i) {
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hp = 1;
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break;
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}
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}
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if (!hp)
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non_perf_lcores[nb_non_perf_lcores++] = i;
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}
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}
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/* update the lcore config */
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for (i = 0; i < nb_prf_lc_prms; i++) {
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int lcore = -1;
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if (prf_lc_prms[i].high_perf) {
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if (prf_lc_prms[i].lcore_idx < nb_hp_lcores)
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lcore = hp_lcores[prf_lc_prms[i].lcore_idx];
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} else {
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if (prf_lc_prms[i].lcore_idx < nb_non_perf_lcores)
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lcore =
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non_perf_lcores[prf_lc_prms[i].lcore_idx];
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}
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if (lcore < 0) {
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printf("Performance cores configuration error\n");
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return -1;
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}
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lcore_params_array[i].lcore_id = lcore;
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lcore_params_array[i].queue_id = prf_lc_prms[i].queue_id;
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lcore_params_array[i].port_id = prf_lc_prms[i].port_id;
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}
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lcore_params = lcore_params_array;
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nb_lcore_params = nb_prf_lc_prms;
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printf("Updated performance core configuration\n");
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for (i = 0; i < nb_prf_lc_prms; i++)
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printf("\t(%d,%d,%d)\n", lcore_params[i].port_id,
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lcore_params[i].queue_id,
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lcore_params[i].lcore_id);
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return 0;
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}
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int
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parse_perf_config(const char *q_arg)
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{
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char s[256];
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const char *p, *p0 = q_arg;
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char *end;
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enum fieldnames {
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FLD_PORT = 0,
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FLD_QUEUE,
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FLD_LCORE_HP,
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FLD_LCORE_IDX,
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_NUM_FLD
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};
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unsigned long int_fld[_NUM_FLD];
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char *str_fld[_NUM_FLD];
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int i;
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unsigned int size;
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nb_prf_lc_prms = 0;
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while ((p = strchr(p0, '(')) != NULL) {
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++p;
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p0 = strchr(p, ')');
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if (p0 == NULL)
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return -1;
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size = p0 - p;
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if (size >= sizeof(s))
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return -1;
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snprintf(s, sizeof(s), "%.*s", size, p);
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if (rte_strsplit(s, sizeof(s), str_fld, _NUM_FLD, ',') !=
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_NUM_FLD)
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return -1;
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for (i = 0; i < _NUM_FLD; i++) {
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errno = 0;
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int_fld[i] = strtoul(str_fld[i], &end, 0);
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if (errno != 0 || end == str_fld[i] || int_fld[i] > 255)
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return -1;
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}
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if (nb_prf_lc_prms >= MAX_LCORE_PARAMS) {
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printf("exceeded max number of lcore params: %hu\n",
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nb_prf_lc_prms);
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return -1;
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}
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prf_lc_prms[nb_prf_lc_prms].port_id =
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(uint8_t)int_fld[FLD_PORT];
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prf_lc_prms[nb_prf_lc_prms].queue_id =
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(uint8_t)int_fld[FLD_QUEUE];
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prf_lc_prms[nb_prf_lc_prms].high_perf =
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!!(uint8_t)int_fld[FLD_LCORE_HP];
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prf_lc_prms[nb_prf_lc_prms].lcore_idx =
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(uint8_t)int_fld[FLD_LCORE_IDX];
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++nb_prf_lc_prms;
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}
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return 0;
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}
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int
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parse_perf_core_list(const char *corelist)
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{
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int i, idx = 0;
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unsigned int count = 0;
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char *end = NULL;
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int min, max;
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if (corelist == NULL) {
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printf("invalid core list\n");
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return -1;
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}
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/* Remove all blank characters ahead and after */
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while (isblank(*corelist))
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corelist++;
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i = strlen(corelist);
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while ((i > 0) && isblank(corelist[i - 1]))
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i--;
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/* Get list of cores */
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min = RTE_MAX_LCORE;
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do {
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while (isblank(*corelist))
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corelist++;
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if (*corelist == '\0')
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return -1;
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errno = 0;
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idx = strtoul(corelist, &end, 10);
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if (errno || end == NULL)
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return -1;
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while (isblank(*end))
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end++;
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if (*end == '-') {
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min = idx;
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} else if ((*end == ',') || (*end == '\0')) {
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max = idx;
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if (min == RTE_MAX_LCORE)
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min = idx;
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for (idx = min; idx <= max; idx++) {
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hp_lcores[count] = idx;
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count++;
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}
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min = RTE_MAX_LCORE;
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} else {
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printf("invalid core list\n");
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return -1;
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}
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corelist = end + 1;
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} while (*end != '\0');
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if (count == 0) {
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printf("invalid core list\n");
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return -1;
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}
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nb_hp_lcores = count;
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printf("Configured %d high performance cores\n", nb_hp_lcores);
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for (i = 0; i < nb_hp_lcores; i++)
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printf("\tHigh performance core %d %d\n",
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i, hp_lcores[i]);
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return 0;
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}
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