2012-12-19 23:00:00 +00:00
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/*******************************************************************************
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2015-06-05 05:21:33 +00:00
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Copyright (c) 2001-2015, Intel Corporation
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2012-12-19 23:00:00 +00:00
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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***************************************************************************/
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#ifndef _IXGBE_DCB_82598_H_
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#define _IXGBE_DCB_82598_H_
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/* DCB register definitions */
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#define IXGBE_DPMCS_MTSOS_SHIFT 16
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#define IXGBE_DPMCS_TDPAC 0x00000001 /* 0 Round Robin,
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* 1 DFP - Deficit Fixed Priority */
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#define IXGBE_DPMCS_TRM 0x00000010 /* Transmit Recycle Mode */
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#define IXGBE_DPMCS_ARBDIS 0x00000040 /* DCB arbiter disable */
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#define IXGBE_DPMCS_TSOEF 0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
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#define IXGBE_RUPPBMR_MQA 0x80000000 /* Enable UP to queue mapping */
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#define IXGBE_RT2CR_MCL_SHIFT 12 /* Offset to Max Credit Limit setting */
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#define IXGBE_RT2CR_LSP 0x80000000 /* LSP enable bit */
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#define IXGBE_RDRXCTL_MPBEN 0x00000010 /* DMA config for multiple packet
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* buffers enable */
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#define IXGBE_RDRXCTL_MCEN 0x00000040 /* DMA config for multiple cores
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* (RSS) enable */
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#define IXGBE_TDTQ2TCCR_MCL_SHIFT 12
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#define IXGBE_TDTQ2TCCR_BWG_SHIFT 9
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#define IXGBE_TDTQ2TCCR_GSP 0x40000000
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#define IXGBE_TDTQ2TCCR_LSP 0x80000000
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#define IXGBE_TDPT2TCCR_MCL_SHIFT 12
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#define IXGBE_TDPT2TCCR_BWG_SHIFT 9
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#define IXGBE_TDPT2TCCR_GSP 0x40000000
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#define IXGBE_TDPT2TCCR_LSP 0x80000000
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#define IXGBE_PDPMCS_TPPAC 0x00000020 /* 0 Round Robin,
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* 1 DFP - Deficit Fixed Priority */
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#define IXGBE_PDPMCS_ARBDIS 0x00000040 /* Arbiter disable */
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#define IXGBE_PDPMCS_TRM 0x00000100 /* Transmit Recycle Mode enable */
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#define IXGBE_DTXCTL_ENDBUBD 0x00000004 /* Enable DBU buffer division */
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#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
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#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */
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#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */
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#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */
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/* DCB driver APIs */
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/* DCB PFC */
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s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8);
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/* DCB stats */
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s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *);
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s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *,
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struct ixgbe_hw_stats *, u8);
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s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *,
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struct ixgbe_hw_stats *, u8);
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/* DCB config arbiters */
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s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
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u8 *, u8 *);
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s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
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u8 *, u8 *);
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s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *);
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/* DCB initialization */
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s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *);
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#endif /* _IXGBE_DCB_82958_H_ */
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