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numam-dpdk/config/defconfig_arm64-octeontx2-linuxapp-gcc

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config: add octeontx2 machine Optimized configuration for Marvell octeontx2 SoC. Updated meson build to support Marvell octeontx2 SoC. Added meson cross build target for octeontx2. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Reviewed-by: Gavin Hu <gavin.hu@arm.com>
2019-04-14 01:49:46 +05:30
# SPDX-License-Identifier: BSD-3-Clause
# Copyright(c) 2018 Marvell International Ltd
#
#include "defconfig_arm64-armv8a-linux-gcc"
CONFIG_RTE_MACHINE="octeontx2"
CONFIG_RTE_MAX_NUMA_NODES=1
CONFIG_RTE_MAX_LCORE=24
eal/arm64: add 128-bit atomic compare exchange This patch adds the implementation of the 128-bit atomic compare exchange API on aarch64. Using 64-bit 'ldxp/stxp' instructions can perform this operation. Moreover, on the LSE atomic extension accelerated platforms, it is implemented by 'casp' instructions for better performance. Since the '__ARM_FEATURE_ATOMICS' flag only supports GCC-9, this patch adds a new config flag 'RTE_ARM_FEATURE_ATOMICS' to enable the 'cas' version on older version compilers. For octeontx2, we make sure that the lse (and other) extensions are enabled even if the compiler does not know of the octeontx2 target cpu. Since direct x0 register used in the code and cas_op_name() and rte_atomic128_cmp_exchange() is inline function, based on parent function load, it may corrupt x0 register aka break aarch64 ABI. Define CAS operations as rte_noinline functions to avoid an ABI break [1]. 1: https://git.dpdk.org/dpdk/commit/?id=5b40ec6b9662 Suggested-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Phil Yang <phil.yang@arm.com> Reviewed-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Tested-by: Honnappa Nagarahalli <honnappa.nagarahalli@arm.com> Acked-by: Jerin Jacob <jerinj@marvell.com> Reviewed-by: David Marchand <david.marchand@redhat.com>
2019-10-18 19:21:28 +08:00
CONFIG_RTE_ARM_FEATURE_ATOMICS=y
config: add octeontx2 machine Optimized configuration for Marvell octeontx2 SoC. Updated meson build to support Marvell octeontx2 SoC. Added meson cross build target for octeontx2. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com> Reviewed-by: Gavin Hu <gavin.hu@arm.com>
2019-04-14 01:49:46 +05:30
# Doesn't support NUMA
CONFIG_RTE_EAL_NUMA_AWARE_HUGEPAGES=n
CONFIG_RTE_LIBRTE_VHOST_NUMA=n
common/octeontx2: add build infrastructure and HW definition Add the make and meson based build infrastructure along with HW definition header file. This patch adds skeleton otx2_mbox.c file to make sure all header files are intact, subsequent patches add content to otx2_mbox.c This patch also updates CONFIG_RTE_MAX_VFIO_GROUPS value to 128 as the system can have up to 128 PFs/VFs. For octeontx2 meson build target, CONFIG_RTE_MAX_VFIO_GROUPS defined as 128 so no additional changes required. Signed-off-by: Jerin Jacob <jerinj@marvell.com> Signed-off-by: Pavan Nikhilesh <pbhagavatula@marvell.com>
2019-06-22 18:53:51 +05:30
# Max supported NIX LFs
CONFIG_RTE_MAX_VFIO_GROUPS=128
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