2018-01-29 13:11:30 +00:00
|
|
|
/* SPDX-License-Identifier: BSD-3-Clause
|
|
|
|
|
* Copyright 2015 6WIND S.A.
|
2018-03-20 19:20:35 +00:00
|
|
|
* Copyright 2015 Mellanox Technologies, Ltd
|
2015-10-30 18:52:31 +00:00
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#ifndef RTE_PMD_MLX5_RXTX_H_
|
|
|
|
|
#define RTE_PMD_MLX5_RXTX_H_
|
|
|
|
|
|
2015-10-30 18:55:09 +00:00
|
|
|
#include <stddef.h>
|
2015-10-30 18:52:31 +00:00
|
|
|
#include <stdint.h>
|
2017-10-09 14:44:45 +00:00
|
|
|
#include <sys/queue.h>
|
2015-10-30 18:52:31 +00:00
|
|
|
|
|
|
|
|
#include <rte_mbuf.h>
|
|
|
|
|
#include <rte_mempool.h>
|
2016-09-20 08:53:47 +00:00
|
|
|
#include <rte_common.h>
|
2017-08-23 07:10:58 +00:00
|
|
|
#include <rte_hexdump.h>
|
2018-07-12 12:01:31 +00:00
|
|
|
#include <rte_spinlock.h>
|
|
|
|
|
#include <rte_io.h>
|
2019-03-10 08:28:02 +00:00
|
|
|
#include <rte_bus_pci.h>
|
2020-07-16 08:23:12 +00:00
|
|
|
#include <rte_cycles.h>
|
2015-10-30 18:52:31 +00:00
|
|
|
|
2020-01-29 12:38:31 +00:00
|
|
|
#include <mlx5_common.h>
|
2020-04-13 21:17:48 +00:00
|
|
|
#include <mlx5_common_mr.h>
|
2020-01-29 12:38:27 +00:00
|
|
|
|
2015-10-30 18:52:31 +00:00
|
|
|
#include "mlx5_utils.h"
|
|
|
|
|
#include "mlx5.h"
|
2015-10-30 18:55:16 +00:00
|
|
|
#include "mlx5_autoconf.h"
|
2020-10-21 20:30:30 +00:00
|
|
|
#include "mlx5_mr.h"
|
2015-10-30 18:52:31 +00:00
|
|
|
|
2019-02-21 09:29:14 +00:00
|
|
|
struct mlx5_priv;
|
2015-10-30 18:52:31 +00:00
|
|
|
|
|
|
|
|
/* mlx5_rxtx.c */
|
|
|
|
|
|
2017-07-26 19:29:33 +00:00
|
|
|
extern uint32_t mlx5_ptype_table[];
|
2018-04-08 12:41:20 +00:00
|
|
|
extern uint8_t mlx5_cksum_table[];
|
|
|
|
|
extern uint8_t mlx5_swp_types_table[];
|
2017-07-06 18:41:10 +00:00
|
|
|
|
2017-07-26 19:29:33 +00:00
|
|
|
void mlx5_set_ptype_table(void);
|
2018-04-08 12:41:20 +00:00
|
|
|
void mlx5_set_cksum_table(void);
|
|
|
|
|
void mlx5_set_swp_types_table(void);
|
2019-05-30 10:20:32 +00:00
|
|
|
void mlx5_dump_debug_information(const char *path, const char *title,
|
|
|
|
|
const void *buf, unsigned int len);
|
2019-05-30 10:20:38 +00:00
|
|
|
int mlx5_queue_state_modify_primary(struct rte_eth_dev *dev,
|
|
|
|
|
const struct mlx5_mp_arg_queue_state_modify *sm);
|
2021-04-12 06:32:21 +00:00
|
|
|
int mlx5_queue_state_modify(struct rte_eth_dev *dev,
|
|
|
|
|
struct mlx5_mp_arg_queue_state_modify *sm);
|
2015-10-30 18:52:31 +00:00
|
|
|
|
net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
|
|
|
/* mlx5_mr.c */
|
|
|
|
|
|
|
|
|
|
void mlx5_mr_flush_local_cache(struct mlx5_mr_ctrl *mr_ctrl);
|
2019-03-10 08:28:02 +00:00
|
|
|
int mlx5_dma_map(struct rte_pci_device *pdev, void *addr, uint64_t iova,
|
|
|
|
|
size_t len);
|
|
|
|
|
int mlx5_dma_unmap(struct rte_pci_device *pdev, void *addr, uint64_t iova,
|
|
|
|
|
size_t len);
|
net/mlx5: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx5_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx5_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx5_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx5_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:04 +00:00
|
|
|
|
2018-09-24 18:36:47 +00:00
|
|
|
/**
|
|
|
|
|
* Get Memory Pool (MP) from mbuf. If mbuf is indirect, the pool from which the
|
|
|
|
|
* cloned mbuf is allocated is returned instead.
|
|
|
|
|
*
|
|
|
|
|
* @param buf
|
|
|
|
|
* Pointer to mbuf.
|
|
|
|
|
*
|
|
|
|
|
* @return
|
|
|
|
|
* Memory pool where data is located for given mbuf.
|
|
|
|
|
*/
|
2018-11-15 10:29:17 +00:00
|
|
|
static inline struct rte_mempool *
|
2018-09-24 18:36:47 +00:00
|
|
|
mlx5_mb2mp(struct rte_mbuf *buf)
|
|
|
|
|
{
|
2019-01-14 05:20:54 +00:00
|
|
|
if (unlikely(RTE_MBUF_CLONED(buf)))
|
2018-09-24 18:36:47 +00:00
|
|
|
return rte_mbuf_from_indirect(buf)->pool;
|
|
|
|
|
return buf->pool;
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-30 18:52:31 +00:00
|
|
|
#endif /* RTE_PMD_MLX5_RXTX_H_ */
|
