net/mlx4: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx4_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx4_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx4_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx4_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:06 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2018 6WIND S.A.
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* Copyright 2018 Mellanox Technologies, Ltd
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*/
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#ifndef RTE_PMD_MLX4_MR_H_
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#define RTE_PMD_MLX4_MR_H_
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#include <stddef.h>
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#include <stdint.h>
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#include <sys/queue.h>
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/* Verbs headers do not support -pedantic. */
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#ifdef PEDANTIC
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#pragma GCC diagnostic ignored "-Wpedantic"
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#endif
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#include <infiniband/verbs.h>
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#ifdef PEDANTIC
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#pragma GCC diagnostic error "-Wpedantic"
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#endif
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#include <rte_ethdev.h>
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#include <rte_rwlock.h>
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#include <rte_bitmap.h>
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/* Size of per-queue MR cache array for linear search. */
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#define MLX4_MR_CACHE_N 8
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/* Size of MR cache table for binary search. */
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#define MLX4_MR_BTREE_CACHE_N 256
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/* Memory Region object. */
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struct mlx4_mr {
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LIST_ENTRY(mlx4_mr) mr; /**< Pointer to the prev/next entry. */
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struct ibv_mr *ibv_mr; /* Verbs Memory Region. */
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const struct rte_memseg_list *msl;
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int ms_base_idx; /* Start index of msl->memseg_arr[]. */
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int ms_n; /* Number of memsegs in use. */
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uint32_t ms_bmp_n; /* Number of bits in memsegs bit-mask. */
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struct rte_bitmap *ms_bmp; /* Bit-mask of memsegs belonged to MR. */
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};
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/* Cache entry for Memory Region. */
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struct mlx4_mr_cache {
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uintptr_t start; /* Start address of MR. */
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uintptr_t end; /* End address of MR. */
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uint32_t lkey; /* rte_cpu_to_be_32(ibv_mr->lkey). */
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} __rte_packed;
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/* MR Cache table for Binary search. */
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struct mlx4_mr_btree {
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uint16_t len; /* Number of entries. */
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uint16_t size; /* Total number of entries. */
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int overflow; /* Mark failure of table expansion. */
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struct mlx4_mr_cache (*table)[];
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} __rte_packed;
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/* Per-queue MR control descriptor. */
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struct mlx4_mr_ctrl {
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uint32_t *dev_gen_ptr; /* Generation number of device to poll. */
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uint32_t cur_gen; /* Generation number saved to flush caches. */
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uint16_t mru; /* Index of last hit entry in top-half cache. */
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uint16_t head; /* Index of the oldest entry in top-half cache. */
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struct mlx4_mr_cache cache[MLX4_MR_CACHE_N]; /* Cache for top-half. */
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struct mlx4_mr_btree cache_bh; /* Cache for bottom-half. */
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} __rte_packed;
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extern struct mlx4_dev_list mlx4_mem_event_cb_list;
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extern rte_rwlock_t mlx4_mem_event_rwlock;
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/* First entry must be NULL for comparison. */
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#define mlx4_mr_btree_len(bt) ((bt)->len - 1)
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int mlx4_mr_btree_init(struct mlx4_mr_btree *bt, int n, int socket);
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void mlx4_mr_btree_free(struct mlx4_mr_btree *bt);
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void mlx4_mr_btree_dump(struct mlx4_mr_btree *bt);
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2019-04-01 21:17:57 +00:00
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uint32_t mlx4_mr_create_primary(struct rte_eth_dev *dev,
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struct mlx4_mr_cache *entry, uintptr_t addr);
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net/mlx4: add new memory region support
This is the new design of Memory Region (MR) for mlx PMD, in order to:
- Accommodate the new memory hotplug model.
- Support non-contiguous Mempool.
There are multiple layers for MR search.
L0 is to look up the last-hit entry which is pointed by mr_ctrl->mru (Most
Recently Used). If L0 misses, L1 is to look up the address in a fixed-sized
array by linear search. L0/L1 is in an inline function -
mlx4_mr_lookup_cache().
If L1 misses, the bottom-half function is called to look up the address
from the bigger local cache of the queue. This is L2 - mlx4_mr_addr2mr_bh()
and it is not an inline function. Data structure for L2 is the Binary Tree.
If L2 misses, the search falls into the slowest path which takes locks in
order to access global device cache (priv->mr.cache) which is also a B-tree
and caches the original MR list (priv->mr.mr_list) of the device. Unless
the global cache is overflowed, it is all-inclusive of the MR list. This is
L3 - mlx4_mr_lookup_dev(). The size of the L3 cache table is limited and
can't be expanded on the fly due to deadlock. Refer to the comments in the
code for the details - mr_lookup_dev(). If L3 is overflowed, the list will
have to be searched directly bypassing the cache although it is slower.
If L3 misses, a new MR for the address should be created -
mlx4_mr_create(). When it creates a new MR, it tries to register adjacent
memsegs as much as possible which are virtually contiguous around the
address. This must take two locks - memory_hotplug_lock and
priv->mr.rwlock. Due to memory_hotplug_lock, there can't be any
allocation/free of memory inside.
In the free callback of the memory hotplug event, freed space is searched
from the MR list and corresponding bits are cleared from the bitmap of MRs.
This can fragment a MR and the MR will have multiple search entries in the
caches. Once there's a change by the event, the global cache must be
rebuilt and all the per-queue caches will be flushed as well. If memory is
frequently freed in run-time, that may cause jitter on dataplane processing
in the worst case by incurring MR cache flush and rebuild. But, it would be
the least probable scenario.
To guarantee the most optimal performance, it is highly recommended to use
an EAL option - '--socket-mem'. Then, the reserved memory will be pinned
and won't be freed dynamically. And it is also recommended to configure
per-lcore cache of Mempool. Even though there're many MRs for a device or
MRs are highly fragmented, the cache of Mempool will be much helpful to
reduce misses on per-queue caches anyway.
'--legacy-mem' is also supported.
Signed-off-by: Yongseok Koh <yskoh@mellanox.com>
2018-05-09 11:09:06 +00:00
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void mlx4_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,
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size_t len, void *arg);
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int mlx4_mr_update_mp(struct rte_eth_dev *dev, struct mlx4_mr_ctrl *mr_ctrl,
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struct rte_mempool *mp);
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void mlx4_mr_dump_dev(struct rte_eth_dev *dev);
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void mlx4_mr_release(struct rte_eth_dev *dev);
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/**
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* Look up LKey from given lookup table by linear search. Firstly look up the
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* last-hit entry. If miss, the entire array is searched. If found, update the
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* last-hit index and return LKey.
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*
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* @param lkp_tbl
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* Pointer to lookup table.
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* @param[in,out] cached_idx
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* Pointer to last-hit index.
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* @param n
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* Size of lookup table.
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* @param addr
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* Search key.
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*
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* @return
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* Searched LKey on success, UINT32_MAX on no match.
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*/
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static __rte_always_inline uint32_t
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mlx4_mr_lookup_cache(struct mlx4_mr_cache *lkp_tbl, uint16_t *cached_idx,
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uint16_t n, uintptr_t addr)
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{
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uint16_t idx;
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if (likely(addr >= lkp_tbl[*cached_idx].start &&
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addr < lkp_tbl[*cached_idx].end))
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return lkp_tbl[*cached_idx].lkey;
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for (idx = 0; idx < n && lkp_tbl[idx].start != 0; ++idx) {
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if (addr >= lkp_tbl[idx].start &&
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addr < lkp_tbl[idx].end) {
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/* Found. */
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*cached_idx = idx;
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return lkp_tbl[idx].lkey;
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}
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}
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return UINT32_MAX;
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}
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#endif /* RTE_PMD_MLX4_MR_H_ */
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