2019-06-26 10:23:09 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright(C) 2019 Marvell International Ltd.
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*/
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#ifndef __OTX2_FLOW_H__
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#define __OTX2_FLOW_H__
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#include <stdint.h>
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#include <rte_flow_driver.h>
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#include <rte_malloc.h>
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#include <rte_tailq.h>
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#include "otx2_common.h"
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#include "otx2_ethdev.h"
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#include "otx2_mbox.h"
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2019-06-26 10:25:03 +00:00
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struct otx2_eth_dev;
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2019-06-26 10:23:09 +00:00
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int otx2_flow_init(struct otx2_eth_dev *hw);
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int otx2_flow_fini(struct otx2_eth_dev *hw);
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extern const struct rte_flow_ops otx2_flow_ops;
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enum {
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OTX2_INTF_RX = 0,
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OTX2_INTF_TX = 1,
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OTX2_INTF_MAX = 2,
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};
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#define NPC_IH_LENGTH 8
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#define NPC_TPID_LENGTH 2
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2019-10-23 15:25:49 +00:00
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#define NPC_HIGIG2_LENGTH 16
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2019-06-26 10:23:09 +00:00
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#define NPC_COUNTER_NONE (-1)
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/* 32 bytes from LDATA_CFG & 32 bytes from FLAGS_CFG */
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#define NPC_MAX_EXTRACT_DATA_LEN (64)
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#define NPC_LDATA_LFLAG_LEN (16)
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#define NPC_MCAM_TOT_ENTRIES (4096)
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#define NPC_MAX_KEY_NIBBLES (31)
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/* Nibble offsets */
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#define NPC_LAYER_KEYX_SZ (3)
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#define NPC_PARSE_KEX_S_LA_OFFSET (7)
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#define NPC_PARSE_KEX_S_LID_OFFSET(lid) \
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((((lid) - NPC_LID_LA) * NPC_LAYER_KEYX_SZ) \
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+ NPC_PARSE_KEX_S_LA_OFFSET)
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/* supported flow actions flags */
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#define OTX2_FLOW_ACT_MARK (1 << 0)
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#define OTX2_FLOW_ACT_FLAG (1 << 1)
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#define OTX2_FLOW_ACT_DROP (1 << 2)
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#define OTX2_FLOW_ACT_QUEUE (1 << 3)
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#define OTX2_FLOW_ACT_RSS (1 << 4)
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#define OTX2_FLOW_ACT_DUP (1 << 5)
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#define OTX2_FLOW_ACT_SEC (1 << 6)
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#define OTX2_FLOW_ACT_COUNT (1 << 7)
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2019-07-08 03:36:15 +00:00
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#define OTX2_FLOW_ACT_PF (1 << 8)
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#define OTX2_FLOW_ACT_VF (1 << 9)
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2020-08-24 07:04:24 +00:00
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#define OTX2_FLOW_ACT_VLAN_STRIP (1 << 10)
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#define OTX2_FLOW_ACT_VLAN_INSERT (1 << 11)
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#define OTX2_FLOW_ACT_VLAN_ETHTYPE_INSERT (1 << 12)
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#define OTX2_FLOW_ACT_VLAN_PCP_INSERT (1 << 13)
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2019-06-26 10:23:09 +00:00
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/* terminating actions */
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#define OTX2_FLOW_ACT_TERM (OTX2_FLOW_ACT_DROP | \
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OTX2_FLOW_ACT_QUEUE | \
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OTX2_FLOW_ACT_RSS | \
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OTX2_FLOW_ACT_DUP | \
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OTX2_FLOW_ACT_SEC)
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/* This mark value indicates flag action */
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#define OTX2_FLOW_FLAG_VAL (0xffff)
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#define NIX_RX_ACT_MATCH_OFFSET (40)
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#define NIX_RX_ACT_MATCH_MASK (0xFFFF)
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#define NIX_RSS_ACT_GRP_OFFSET (20)
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#define NIX_RSS_ACT_ALG_OFFSET (56)
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#define NIX_RSS_ACT_GRP_MASK (0xFFFFF)
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#define NIX_RSS_ACT_ALG_MASK (0x1F)
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/* PMD-specific definition of the opaque struct rte_flow */
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#define OTX2_MAX_MCAM_WIDTH_DWORDS 7
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enum npc_mcam_intf {
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NPC_MCAM_RX,
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NPC_MCAM_TX
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};
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struct npc_xtract_info {
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/* Length in bytes of pkt data extracted. len = 0
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* indicates that extraction is disabled.
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*/
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uint8_t len;
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uint8_t hdr_off; /* Byte offset of proto hdr: extract_src */
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uint8_t key_off; /* Byte offset in MCAM key where data is placed */
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uint8_t enable; /* Extraction enabled or disabled */
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2019-07-15 05:05:55 +00:00
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uint8_t flags_enable; /* Flags extraction enabled */
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2019-06-26 10:23:09 +00:00
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};
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/* Information for a given {LAYER, LTYPE} */
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struct npc_lid_lt_xtract_info {
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/* Info derived from parser configuration */
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uint16_t npc_proto; /* Network protocol identified */
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uint8_t valid_flags_mask; /* Flags applicable */
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uint8_t is_terminating:1; /* No more parsing */
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struct npc_xtract_info xtract[NPC_MAX_LD];
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};
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union npc_kex_ldata_flags_cfg {
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struct {
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#if defined(__BIG_ENDIAN_BITFIELD)
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uint64_t rvsd_62_1 : 61;
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uint64_t lid : 3;
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#else
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uint64_t lid : 3;
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uint64_t rvsd_62_1 : 61;
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#endif
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} s;
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uint64_t i;
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};
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typedef struct npc_lid_lt_xtract_info
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otx2_dxcfg_t[NPC_MAX_INTF][NPC_MAX_LID][NPC_MAX_LT];
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typedef struct npc_lid_lt_xtract_info
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otx2_fxcfg_t[NPC_MAX_INTF][NPC_MAX_LD][NPC_MAX_LFL];
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typedef union npc_kex_ldata_flags_cfg otx2_ld_flags_t[NPC_MAX_LD];
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/* MBOX_MSG_NPC_GET_DATAX_CFG Response */
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struct npc_get_datax_cfg {
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/* NPC_AF_KEX_LDATA(0..1)_FLAGS_CFG */
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union npc_kex_ldata_flags_cfg ld_flags[NPC_MAX_LD];
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/* Extract information indexed with [LID][LTYPE] */
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struct npc_lid_lt_xtract_info lid_lt_xtract[NPC_MAX_LID][NPC_MAX_LT];
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/* Flags based extract indexed with [LDATA][FLAGS_LOWER_NIBBLE]
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* Fields flags_ena_ld0, flags_ena_ld1 in
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* struct npc_lid_lt_xtract_info indicate if this is applicable
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* for a given {LAYER, LTYPE}
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*/
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struct npc_xtract_info flag_xtract[NPC_MAX_LD][NPC_MAX_LT];
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};
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struct otx2_mcam_ents_info {
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/* Current max & min values of mcam index */
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uint32_t max_id;
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uint32_t min_id;
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uint32_t free_ent;
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uint32_t live_ent;
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};
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net/octeontx2: support flow API dump
Add support to dump hardware internal representation information of
rte flow to file.
Every flow rule added will be dumped in the below format.
MCAM Index:1881
Interface :NIX-RX (0)
Priority :1
NPC RX Action:0X00000000404001
ActionOp:NIX_RX_ACTIONOP_UCAST (1)
PF_FUNC: 0X400
RQ Index:0X004
Match Id:0000
Flow Key Alg:0
NPC RX VTAG Action:0X00000000008100
VTAG0:relptr:0
lid:0X1
type:0
Patterns:
NPC_PARSE_NIBBLE_CHAN:000
NPC_PARSE_NIBBLE_LA_LTYPE:LA_ETHER
NPC_PARSE_NIBBLE_LB_LTYPE:NONE
NPC_PARSE_NIBBLE_LC_LTYPE:LC_IP
NPC_PARSE_NIBBLE_LD_LTYPE:LD_TCP
NPC_PARSE_NIBBLE_LE_LTYPE:NONE
LA_ETHER, hdr offset:0, len:0X6, key offset:0X8,\
Data:0X4AE124FC7FFF, Mask:0XFFFFFFFFFFFF
LA_ETHER, hdr offset:0XC, len:0X2, key offset:0X4, Data:0XCA5A,\
Mask:0XFFFF
LC_IP, hdr offset:0XC, len:0X8, key offset:0X10,\
Data:0X0A01010300000000, Mask:0XFFFFFFFF00000000
LD_TCP, hdr offset:0, len:0X4, key offset:0X18, Data:0X03450000,\
Mask:0XFFFF0000
MCAM Raw Data :
DW0 :0000CA5A01202000
DW0_Mask:0000FFFF0FF0F000
DW1 :00004AE124FC7FFF
DW1_Mask:0000FFFFFFFFFFFF
DW2 :0A01010300000000
DW2_Mask:FFFFFFFF00000000
DW3 :0000000003450000
DW3_Mask:00000000FFFF0000
DW4 :0000000000000000
DW4_Mask:0000000000000000
DW5 :0000000000000000
DW5_Mask:0000000000000000
DW6 :0000000000000000
DW6_Mask:0000000000000000
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-02-08 13:01:57 +00:00
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struct otx2_flow_dump_data {
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uint8_t lid;
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uint16_t ltype;
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};
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2019-06-26 10:23:09 +00:00
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struct rte_flow {
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uint8_t nix_intf;
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uint32_t mcam_id;
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int32_t ctr_id;
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uint32_t priority;
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/* Contiguous match string */
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uint64_t mcam_data[OTX2_MAX_MCAM_WIDTH_DWORDS];
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uint64_t mcam_mask[OTX2_MAX_MCAM_WIDTH_DWORDS];
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uint64_t npc_action;
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2020-08-24 07:04:24 +00:00
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uint64_t vtag_action;
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net/octeontx2: support flow API dump
Add support to dump hardware internal representation information of
rte flow to file.
Every flow rule added will be dumped in the below format.
MCAM Index:1881
Interface :NIX-RX (0)
Priority :1
NPC RX Action:0X00000000404001
ActionOp:NIX_RX_ACTIONOP_UCAST (1)
PF_FUNC: 0X400
RQ Index:0X004
Match Id:0000
Flow Key Alg:0
NPC RX VTAG Action:0X00000000008100
VTAG0:relptr:0
lid:0X1
type:0
Patterns:
NPC_PARSE_NIBBLE_CHAN:000
NPC_PARSE_NIBBLE_LA_LTYPE:LA_ETHER
NPC_PARSE_NIBBLE_LB_LTYPE:NONE
NPC_PARSE_NIBBLE_LC_LTYPE:LC_IP
NPC_PARSE_NIBBLE_LD_LTYPE:LD_TCP
NPC_PARSE_NIBBLE_LE_LTYPE:NONE
LA_ETHER, hdr offset:0, len:0X6, key offset:0X8,\
Data:0X4AE124FC7FFF, Mask:0XFFFFFFFFFFFF
LA_ETHER, hdr offset:0XC, len:0X2, key offset:0X4, Data:0XCA5A,\
Mask:0XFFFF
LC_IP, hdr offset:0XC, len:0X8, key offset:0X10,\
Data:0X0A01010300000000, Mask:0XFFFFFFFF00000000
LD_TCP, hdr offset:0, len:0X4, key offset:0X18, Data:0X03450000,\
Mask:0XFFFF0000
MCAM Raw Data :
DW0 :0000CA5A01202000
DW0_Mask:0000FFFF0FF0F000
DW1 :00004AE124FC7FFF
DW1_Mask:0000FFFFFFFFFFFF
DW2 :0A01010300000000
DW2_Mask:FFFFFFFF00000000
DW3 :0000000003450000
DW3_Mask:00000000FFFF0000
DW4 :0000000000000000
DW4_Mask:0000000000000000
DW5 :0000000000000000
DW5_Mask:0000000000000000
DW6 :0000000000000000
DW6_Mask:0000000000000000
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-02-08 13:01:57 +00:00
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struct otx2_flow_dump_data dump_data[32];
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uint16_t num_patterns;
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2019-06-26 10:23:09 +00:00
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TAILQ_ENTRY(rte_flow) next;
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};
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TAILQ_HEAD(otx2_flow_list, rte_flow);
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/* Accessed from ethdev private - otx2_eth_dev */
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struct otx2_npc_flow_info {
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rte_atomic32_t mark_actions;
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2020-08-24 07:04:24 +00:00
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uint32_t vtag_actions;
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2019-06-26 10:23:09 +00:00
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uint32_t keyx_supp_nmask[NPC_MAX_INTF];/* nibble mask */
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uint32_t keyx_len[NPC_MAX_INTF]; /* per intf key len in bits */
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uint32_t datax_len[NPC_MAX_INTF]; /* per intf data len in bits */
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uint32_t keyw[NPC_MAX_INTF]; /* max key + data len bits */
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uint32_t mcam_entries; /* mcam entries supported */
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otx2_dxcfg_t prx_dxcfg; /* intf, lid, lt, extract */
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otx2_fxcfg_t prx_fxcfg; /* Flag extract */
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otx2_ld_flags_t prx_lfcfg; /* KEX LD_Flags CFG */
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/* mcam entry info per priority level: both free & in-use */
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struct otx2_mcam_ents_info *flow_entry_info;
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/* Bitmap of free preallocated entries in ascending index &
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* descending priority
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*/
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struct rte_bitmap **free_entries;
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/* Bitmap of free preallocated entries in descending index &
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* ascending priority
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*/
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struct rte_bitmap **free_entries_rev;
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/* Bitmap of live entries in ascending index & descending priority */
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struct rte_bitmap **live_entries;
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/* Bitmap of live entries in descending index & ascending priority */
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struct rte_bitmap **live_entries_rev;
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/* Priority bucket wise tail queue of all rte_flow resources */
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struct otx2_flow_list *flow_list;
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uint32_t rss_grps; /* rss groups supported */
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struct rte_bitmap *rss_grp_entries;
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uint16_t channel; /*rx channel */
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uint16_t flow_prealloc_size;
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uint16_t flow_max_priority;
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2019-10-23 15:25:48 +00:00
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uint16_t switch_header_type;
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2019-06-26 10:23:09 +00:00
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};
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struct otx2_parse_state {
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struct otx2_npc_flow_info *npc;
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const struct rte_flow_item *pattern;
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const struct rte_flow_item *last_pattern; /* Temp usage */
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struct rte_flow_error *error;
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struct rte_flow *flow;
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uint8_t tunnel;
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uint8_t terminate;
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uint8_t layer_mask;
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uint8_t lt[NPC_MAX_LID];
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uint8_t flags[NPC_MAX_LID];
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uint8_t *mcam_data; /* point to flow->mcam_data + key_len */
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uint8_t *mcam_mask; /* point to flow->mcam_mask + key_len */
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2020-10-21 03:31:31 +00:00
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bool is_vf;
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2019-06-26 10:23:09 +00:00
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};
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struct otx2_flow_item_info {
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const void *def_mask; /* rte_flow default mask */
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void *hw_mask; /* hardware supported mask */
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int len; /* length of item */
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const void *spec; /* spec to use, NULL implies match any */
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const void *mask; /* mask to use */
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uint8_t hw_hdr_len; /* Extra data len at each layer*/
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};
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struct otx2_idev_kex_cfg {
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struct npc_get_kex_cfg_rsp kex_cfg;
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rte_atomic16_t kex_refcnt;
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};
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enum npc_kpu_parser_flag {
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NPC_F_NA = 0,
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NPC_F_PKI,
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NPC_F_PKI_VLAN,
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NPC_F_PKI_ETAG,
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NPC_F_PKI_ITAG,
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NPC_F_PKI_MPLS,
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NPC_F_PKI_NSH,
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NPC_F_ETYPE_UNK,
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NPC_F_ETHER_VLAN,
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NPC_F_ETHER_ETAG,
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NPC_F_ETHER_ITAG,
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NPC_F_ETHER_MPLS,
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NPC_F_ETHER_NSH,
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NPC_F_STAG_CTAG,
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NPC_F_STAG_CTAG_UNK,
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NPC_F_STAG_STAG_CTAG,
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NPC_F_STAG_STAG_STAG,
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NPC_F_QINQ_CTAG,
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NPC_F_QINQ_CTAG_UNK,
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NPC_F_QINQ_QINQ_CTAG,
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NPC_F_QINQ_QINQ_QINQ,
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NPC_F_BTAG_ITAG,
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NPC_F_BTAG_ITAG_STAG,
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NPC_F_BTAG_ITAG_CTAG,
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NPC_F_BTAG_ITAG_UNK,
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NPC_F_ETAG_CTAG,
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NPC_F_ETAG_BTAG_ITAG,
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NPC_F_ETAG_STAG,
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NPC_F_ETAG_QINQ,
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NPC_F_ETAG_ITAG,
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NPC_F_ETAG_ITAG_STAG,
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NPC_F_ETAG_ITAG_CTAG,
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NPC_F_ETAG_ITAG_UNK,
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NPC_F_ITAG_STAG_CTAG,
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NPC_F_ITAG_STAG,
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NPC_F_ITAG_CTAG,
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NPC_F_MPLS_4_LABELS,
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NPC_F_MPLS_3_LABELS,
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NPC_F_MPLS_2_LABELS,
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NPC_F_IP_HAS_OPTIONS,
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NPC_F_IP_IP_IN_IP,
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NPC_F_IP_6TO4,
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NPC_F_IP_MPLS_IN_IP,
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NPC_F_IP_UNK_PROTO,
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NPC_F_IP_IP_IN_IP_HAS_OPTIONS,
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NPC_F_IP_6TO4_HAS_OPTIONS,
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NPC_F_IP_MPLS_IN_IP_HAS_OPTIONS,
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NPC_F_IP_UNK_PROTO_HAS_OPTIONS,
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NPC_F_IP6_HAS_EXT,
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NPC_F_IP6_TUN_IP6,
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NPC_F_IP6_MPLS_IN_IP,
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NPC_F_TCP_HAS_OPTIONS,
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NPC_F_TCP_HTTP,
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NPC_F_TCP_HTTPS,
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NPC_F_TCP_PPTP,
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NPC_F_TCP_UNK_PORT,
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NPC_F_TCP_HTTP_HAS_OPTIONS,
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NPC_F_TCP_HTTPS_HAS_OPTIONS,
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NPC_F_TCP_PPTP_HAS_OPTIONS,
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NPC_F_TCP_UNK_PORT_HAS_OPTIONS,
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NPC_F_UDP_VXLAN,
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NPC_F_UDP_VXLAN_NOVNI,
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NPC_F_UDP_VXLAN_NOVNI_NSH,
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NPC_F_UDP_VXLANGPE,
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NPC_F_UDP_VXLANGPE_NSH,
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NPC_F_UDP_VXLANGPE_MPLS,
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NPC_F_UDP_VXLANGPE_NOVNI,
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NPC_F_UDP_VXLANGPE_NOVNI_NSH,
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NPC_F_UDP_VXLANGPE_NOVNI_MPLS,
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NPC_F_UDP_VXLANGPE_UNK,
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NPC_F_UDP_VXLANGPE_NONP,
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NPC_F_UDP_GTP_GTPC,
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NPC_F_UDP_GTP_GTPU_G_PDU,
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NPC_F_UDP_GTP_GTPU_UNK,
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NPC_F_UDP_UNK_PORT,
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NPC_F_UDP_GENEVE,
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NPC_F_UDP_GENEVE_OAM,
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NPC_F_UDP_GENEVE_CRI_OPT,
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NPC_F_UDP_GENEVE_OAM_CRI_OPT,
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NPC_F_GRE_NVGRE,
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NPC_F_GRE_HAS_SRE,
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NPC_F_GRE_HAS_CSUM,
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NPC_F_GRE_HAS_KEY,
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|
NPC_F_GRE_HAS_SEQ,
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|
NPC_F_GRE_HAS_CSUM_KEY,
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|
NPC_F_GRE_HAS_CSUM_SEQ,
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|
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|
NPC_F_GRE_HAS_KEY_SEQ,
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|
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|
NPC_F_GRE_HAS_CSUM_KEY_SEQ,
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|
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|
NPC_F_GRE_HAS_ROUTE,
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|
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|
NPC_F_GRE_UNK_PROTO,
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|
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|
NPC_F_GRE_VER1,
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|
|
|
NPC_F_GRE_VER1_HAS_SEQ,
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|
|
|
NPC_F_GRE_VER1_HAS_ACK,
|
|
|
|
NPC_F_GRE_VER1_HAS_SEQ_ACK,
|
|
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|
NPC_F_GRE_VER1_UNK_PROTO,
|
|
|
|
NPC_F_TU_ETHER_UNK,
|
|
|
|
NPC_F_TU_ETHER_CTAG,
|
|
|
|
NPC_F_TU_ETHER_CTAG_UNK,
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|
|
|
NPC_F_TU_ETHER_STAG_CTAG,
|
|
|
|
NPC_F_TU_ETHER_STAG_CTAG_UNK,
|
|
|
|
NPC_F_TU_ETHER_STAG,
|
|
|
|
NPC_F_TU_ETHER_STAG_UNK,
|
|
|
|
NPC_F_TU_ETHER_QINQ_CTAG,
|
|
|
|
NPC_F_TU_ETHER_QINQ_CTAG_UNK,
|
|
|
|
NPC_F_TU_ETHER_QINQ,
|
|
|
|
NPC_F_TU_ETHER_QINQ_UNK,
|
|
|
|
NPC_F_LAST /* has to be the last item */
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
int otx2_flow_mcam_free_counter(struct otx2_mbox *mbox, uint16_t ctr_id);
|
|
|
|
|
|
|
|
int otx2_flow_mcam_read_counter(struct otx2_mbox *mbox, uint32_t ctr_id,
|
|
|
|
uint64_t *count);
|
|
|
|
|
|
|
|
int otx2_flow_mcam_clear_counter(struct otx2_mbox *mbox, uint32_t ctr_id);
|
|
|
|
|
|
|
|
int otx2_flow_mcam_free_entry(struct otx2_mbox *mbox, uint32_t entry);
|
|
|
|
|
|
|
|
int otx2_flow_mcam_free_all_entries(struct otx2_mbox *mbox);
|
|
|
|
|
|
|
|
int otx2_flow_update_parse_state(struct otx2_parse_state *pst,
|
|
|
|
struct otx2_flow_item_info *info,
|
|
|
|
int lid, int lt, uint8_t flags);
|
|
|
|
|
|
|
|
int otx2_flow_parse_item_basic(const struct rte_flow_item *item,
|
|
|
|
struct otx2_flow_item_info *info,
|
|
|
|
struct rte_flow_error *error);
|
|
|
|
|
|
|
|
void otx2_flow_keyx_compress(uint64_t *data, uint32_t nibble_mask);
|
|
|
|
|
|
|
|
int otx2_flow_mcam_alloc_and_write(struct rte_flow *flow,
|
|
|
|
struct otx2_mbox *mbox,
|
|
|
|
struct otx2_parse_state *pst,
|
|
|
|
struct otx2_npc_flow_info *flow_info);
|
|
|
|
|
|
|
|
void otx2_flow_get_hw_supp_mask(struct otx2_parse_state *pst,
|
|
|
|
struct otx2_flow_item_info *info,
|
|
|
|
int lid, int lt);
|
|
|
|
|
|
|
|
const struct rte_flow_item *
|
|
|
|
otx2_flow_skip_void_and_any_items(const struct rte_flow_item *pattern);
|
|
|
|
|
|
|
|
int otx2_flow_parse_lh(struct otx2_parse_state *pst);
|
|
|
|
|
|
|
|
int otx2_flow_parse_lg(struct otx2_parse_state *pst);
|
|
|
|
|
|
|
|
int otx2_flow_parse_lf(struct otx2_parse_state *pst);
|
|
|
|
|
|
|
|
int otx2_flow_parse_le(struct otx2_parse_state *pst);
|
|
|
|
|
|
|
|
int otx2_flow_parse_ld(struct otx2_parse_state *pst);
|
|
|
|
|
|
|
|
int otx2_flow_parse_lc(struct otx2_parse_state *pst);
|
|
|
|
|
|
|
|
int otx2_flow_parse_lb(struct otx2_parse_state *pst);
|
|
|
|
|
|
|
|
int otx2_flow_parse_la(struct otx2_parse_state *pst);
|
|
|
|
|
2019-10-23 15:25:49 +00:00
|
|
|
int otx2_flow_parse_higig2_hdr(struct otx2_parse_state *pst);
|
|
|
|
|
2019-06-26 10:23:09 +00:00
|
|
|
int otx2_flow_parse_actions(struct rte_eth_dev *dev,
|
|
|
|
const struct rte_flow_attr *attr,
|
|
|
|
const struct rte_flow_action actions[],
|
|
|
|
struct rte_flow_error *error,
|
|
|
|
struct rte_flow *flow);
|
|
|
|
|
|
|
|
int otx2_flow_free_all_resources(struct otx2_eth_dev *hw);
|
|
|
|
|
|
|
|
int otx2_flow_parse_mpls(struct otx2_parse_state *pst, int lid);
|
net/octeontx2: support flow API dump
Add support to dump hardware internal representation information of
rte flow to file.
Every flow rule added will be dumped in the below format.
MCAM Index:1881
Interface :NIX-RX (0)
Priority :1
NPC RX Action:0X00000000404001
ActionOp:NIX_RX_ACTIONOP_UCAST (1)
PF_FUNC: 0X400
RQ Index:0X004
Match Id:0000
Flow Key Alg:0
NPC RX VTAG Action:0X00000000008100
VTAG0:relptr:0
lid:0X1
type:0
Patterns:
NPC_PARSE_NIBBLE_CHAN:000
NPC_PARSE_NIBBLE_LA_LTYPE:LA_ETHER
NPC_PARSE_NIBBLE_LB_LTYPE:NONE
NPC_PARSE_NIBBLE_LC_LTYPE:LC_IP
NPC_PARSE_NIBBLE_LD_LTYPE:LD_TCP
NPC_PARSE_NIBBLE_LE_LTYPE:NONE
LA_ETHER, hdr offset:0, len:0X6, key offset:0X8,\
Data:0X4AE124FC7FFF, Mask:0XFFFFFFFFFFFF
LA_ETHER, hdr offset:0XC, len:0X2, key offset:0X4, Data:0XCA5A,\
Mask:0XFFFF
LC_IP, hdr offset:0XC, len:0X8, key offset:0X10,\
Data:0X0A01010300000000, Mask:0XFFFFFFFF00000000
LD_TCP, hdr offset:0, len:0X4, key offset:0X18, Data:0X03450000,\
Mask:0XFFFF0000
MCAM Raw Data :
DW0 :0000CA5A01202000
DW0_Mask:0000FFFF0FF0F000
DW1 :00004AE124FC7FFF
DW1_Mask:0000FFFFFFFFFFFF
DW2 :0A01010300000000
DW2_Mask:FFFFFFFF00000000
DW3 :0000000003450000
DW3_Mask:00000000FFFF0000
DW4 :0000000000000000
DW4_Mask:0000000000000000
DW5 :0000000000000000
DW5_Mask:0000000000000000
DW6 :0000000000000000
DW6_Mask:0000000000000000
Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
2021-02-08 13:01:57 +00:00
|
|
|
|
|
|
|
void otx2_flow_dump(FILE *file, struct otx2_eth_dev *hw,
|
|
|
|
struct rte_flow *flow);
|
2019-06-26 10:23:09 +00:00
|
|
|
#endif /* __OTX2_FLOW_H__ */
|