2017-10-09 18:46:56 +00:00
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/*-
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* BSD LICENSE
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*
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* Copyright 2017 6WIND S.A.
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* Copyright 2017 Mellanox.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of 6WIND S.A. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef RTE_PMD_MLX5_RXTX_VEC_H_
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#define RTE_PMD_MLX5_RXTX_VEC_H_
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#include <rte_common.h>
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#include <rte_mbuf.h>
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#include "mlx5_autoconf.h"
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#include "mlx5_prm.h"
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/*
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* Compile time sanity check for vectorized functions.
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*/
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#define S_ASSERT_RTE_MBUF(s) \
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static_assert(s, "A field of struct rte_mbuf is changed")
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#define S_ASSERT_MLX5_CQE(s) \
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static_assert(s, "A field of struct mlx5_cqe is changed")
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/* rxq_cq_decompress_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, hash) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
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/* rxq_cq_to_ptype_oflags_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, ol_flags) ==
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offsetof(struct rte_mbuf, rearm_data) + 8);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, rearm_data) ==
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RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
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/* rxq_burst_v() */
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, pkt_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
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S_ASSERT_RTE_MBUF(offsetof(struct rte_mbuf, data_len) ==
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offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, pkt_info) == 0);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rx_hash_res) ==
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offsetof(struct mlx5_cqe, pkt_info) + 12);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rsvd1) +
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sizeof(((struct mlx5_cqe *)0)->rsvd1) ==
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offsetof(struct mlx5_cqe, hdr_type_etc));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, vlan_info) ==
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offsetof(struct mlx5_cqe, hdr_type_etc) + 2);
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, rsvd2) +
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sizeof(((struct mlx5_cqe *)0)->rsvd2) ==
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offsetof(struct mlx5_cqe, byte_cnt));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, sop_drop_qpn) ==
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RTE_ALIGN(offsetof(struct mlx5_cqe, sop_drop_qpn), 8));
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S_ASSERT_MLX5_CQE(offsetof(struct mlx5_cqe, op_own) ==
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offsetof(struct mlx5_cqe, sop_drop_qpn) + 7);
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2017-10-09 18:46:57 +00:00
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/**
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* Replenish buffers for RX in bulk.
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*
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* @param rxq
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* Pointer to RX queue structure.
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* @param n
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* Number of buffers to be replenished.
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*/
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static inline void
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mlx5_rx_replenish_bulk_mbuf(struct mlx5_rxq_data *rxq, uint16_t n)
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{
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const uint16_t q_n = 1 << rxq->elts_n;
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const uint16_t q_mask = q_n - 1;
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const uint16_t elts_idx = rxq->rq_ci & q_mask;
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struct rte_mbuf **elts = &(*rxq->elts)[elts_idx];
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volatile struct mlx5_wqe_data_seg *wq = &(*rxq->wqes)[elts_idx];
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unsigned int i;
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assert(n >= MLX5_VPMD_RXQ_RPLNSH_THRESH);
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assert(n <= (uint16_t)(q_n - (rxq->rq_ci - rxq->rq_pi)));
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assert(MLX5_VPMD_RXQ_RPLNSH_THRESH > MLX5_VPMD_DESCS_PER_LOOP);
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/* Not to cross queue end. */
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n = RTE_MIN(n - MLX5_VPMD_DESCS_PER_LOOP, q_n - elts_idx);
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if (rte_mempool_get_bulk(rxq->mp, (void *)elts, n) < 0) {
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rxq->stats.rx_nombuf += n;
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return;
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}
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for (i = 0; i < n; ++i)
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wq[i].addr = rte_cpu_to_be_64((uintptr_t)elts[i]->buf_addr +
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RTE_PKTMBUF_HEADROOM);
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rxq->rq_ci += n;
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rte_io_wmb();
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*rxq->rq_db = rte_cpu_to_be_32(rxq->rq_ci);
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}
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2017-10-09 18:46:56 +00:00
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#endif /* RTE_PMD_MLX5_RXTX_VEC_H_ */
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