2019-10-10 06:32:22 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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* Copyright 2019 NXP
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*/
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#ifndef _PFE_ETH_H_
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#define _PFE_ETH_H_
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#include <compat.h>
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#include <rte_ethdev.h>
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#include <rte_ethdev_vdev.h>
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#define ETH_ALEN 6
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#define GEMAC_NO_PHY BIT(0)
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#define PFE_SOC_ID_FILE "/sys/devices/soc0/soc_id"
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extern unsigned int pfe_svr;
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#define SVR_LS1012A_REV2 0x87040020
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#define SVR_LS1012A_REV1 0x87040010
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2019-10-10 06:32:26 +00:00
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#define PFE_ETH_OVERHEAD (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN)
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#define MAX_MTU_ON_REV1 1878
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2019-10-10 06:32:22 +00:00
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struct ls1012a_eth_platform_data {
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/* device specific information */
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u32 device_flags;
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char name[16];
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/* board specific information */
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u32 mii_config;
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u32 phy_flags;
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u32 gem_id;
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u32 bus_id;
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u32 phy_id;
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u32 mdio_muxval;
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u8 mac_addr[ETH_ALEN];
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};
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struct ls1012a_mdio_platform_data {
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int enabled;
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int irq[32];
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u32 phy_mask;
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int mdc_div;
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};
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struct ls1012a_pfe_platform_data {
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struct ls1012a_eth_platform_data ls1012a_eth_pdata[3];
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struct ls1012a_mdio_platform_data ls1012a_mdio_pdata[3];
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};
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#define EMAC_TXQ_CNT 16
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#define EMAC_TXQ_DEPTH (HIF_TX_DESC_NT)
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#define JUMBO_FRAME_SIZE 10258
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#define EMAC_RXQ_CNT 1
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#define EMAC_RXQ_DEPTH HIF_RX_DESC_NT
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struct pfe_eth_priv_s {
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struct pfe *pfe;
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int low_tmu_q;
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int high_tmu_q;
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struct rte_eth_dev *ndev;
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struct rte_eth_stats stats;
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int id;
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int promisc;
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int link_fd;
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spinlock_t lock; /* protect member variables */
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void *EMAC_baseaddr;
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/* This points to the EMAC base from where we access PHY */
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void *PHY_baseaddr;
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void *GPI_baseaddr;
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struct ls1012a_eth_platform_data *einfo;
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};
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#endif /* _PFE_ETH_H_ */
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